4 Channel SPI

Hi,

I just found out that this is a better place to ask my question, it seams like there is also a beaglebone Google group, little confusing. So here my cross-post:

I’d like to connect 4 ADS85280 daisy-chained via SPI to a BBB. I want to test it in different iterations first I want to measure the 32 Analog input channels captured by the ADS8528s with 1kHz and at the end with 200kHz. Those ADS8528 using 4 SPI Channels in daisy-chain mode. So I did some calculations on the needed bandwidth:

for 1Khz:

12Bit * 32Channels * 4KHz = 384 Kbit/s

On 4 SPI Channels that means:
12* 32*1Khz = 96 Kbit/s per SPI channel

for 200Khz:

12Bit * 32Channels * 200KHz = 76.8 Mbit/s = 9.6MByte/s

On 4 SPI Channels that means:
76.8Mb/s /4 = 19.2 Mbit/s per SPI channel

Now 2 things:

  • Should/Can I use the built-in SPI of the BBB or do I have to implement 4 channels SPI bus by hand (High datarates PRUSS I guess)?
  • Do you think the high datarates for the 200Khz are achievable?

Thanks,

/Julian

This is the correct place to ask…

Gerald

I think you might have to do this in a PRU: I believe the SPI clock divider input runs at 48 MHz, so it can divide down to 24 MHz, 16 MHz, 12 MHz, etc. But I have also read someplace that it doesn’t work above 16 MHz. You should also keep in mind that the SPI device driver takes the passed speed parameter as “maximum speed”, and so might actually run at a lower clock speed than you believe you requested.

So if you get SPI really running at 16 MHz, you would still have to run SPI0 and SPI1 interfaces in parallel with half your ADCs on each interface. Or you could do it by bit-banging GPIOs to talk to each ADC separately using a PRU.

As to the feasibility of doing it in the ARM processor: I think you can do this easily in the AM3359 bare metal, but maybe not in the Linux environment. Without realtime patches, you get 10-100 msec maximum latency. With exactly the right kernel mods I think you can get interrupt drivers to respond in a max of 50 usecs. But this is precisely why TI included the PRUs.

Hi,

I just found out that this is a better place to ask my question, it seams like there is also a beaglebone Google group, little confusing. So here my cross-post:

I’d like to connect 4 ADS8528[0] daisy-chained via SPI to a BBB. I want to test it in different iterations first I want to measure the 32 Analog input channels captured by the ADS8528s with 1kHz and at the end with 200kHz. Those ADS8528 using 4 SPI Channels in daisy-chain mode. So I did some calculations on the needed bandwidth:

for 1Khz:

12Bit * 32Channels * 4KHz = 384 Kbit/s

On 4 SPI Channels that means:
12* 32*1Khz = 96 Kbit/s per SPI channel

for 200Khz:

12Bit * 32Channels * 200KHz = 76.8 Mbit/s = 9.6MByte/s

On 4 SPI Channels that means:
76.8Mb/s /4 = 19.2 Mbit/s per SPI channel

Now 2 things:

  • Should/Can I use the built-in SPI of the BBB or do I have to implement 4 channels SPI bus by hand (High datarates PRUSS I guess)?
  • Do you think the high datarates for the 200Khz are achievable?

While SPI can achieve the bandwidth you require, I’m not sure you will get this to work without a kernel driver given that the message transfers are small so DMA won’t be used. You may want to ask this question on the Linux-IIO forum.

Regards,
John

Hello Julian,
I am having the same issue, could you let me know about the solution? Have you found some workaround to use BBB->SPI and ADS8528?

Best regards
Antonio

Hej Antonio,

I used the PRU to communicate with the BBB, which works quite good.
But datarates with more the 20 Mbit are not realistic since the PRUs
have a clock of 200 Mhz.
If you are interested I could prepare some code to release.

bests,

Julian

Hello Julian

Thank you for your fast reply.
I am trying to use the same ADS8528 to read 48 channel of sensors using daisy-chain to get the information simultaneously.
Definitely I appreciate if you can send me some code.

Best regards,
Antonio

What is your planned sample frequency?

something around 450kS/s

It will be impossible to do that with that amount of channels. Each
sample has 16 bit.

48 Channels * 450 kS/s * 16 bit = 345.6 Mbit/S.

Besides that is probably beyond any bus speed on the SoC. It would as
well require you to interface with 24 SPI lines in parallel in full
speed. There is absolutely no way to do that on a BeagleBone. You'll
have to go for a FPGA or a faster ADC with analog multiplexing in you
front-end.

Bests,

Julian

Indeed, you are right. in the BBB I will test the concept with small frequency , like 4.5kS/s with 3.3MBit/S