I struggled to find an easy reference for determining pin mux settings to be used in the ‘am335x_bone-common.dtsi’ device tree file, so I thought I’d document the process for others:
All references below are to the ‘AM335x ARM® Cortex™-A8 Microprocessors
(MPUs) - Technical Reference Manual’ (spruh73h.pdf).
Beginning from section ‘2.1 ARM Cortex-A8 Memory Map’ (pg. 155), we find, in the table ‘Table 2-1. L3 Memory Map’ a reference to the section ‘L4_WKUP’ with a given memory range of ‘0x44C0_0000 0x44FF_FFFF’.
Looking at the table ‘Table 2-2. L4_WKUP Peripheral Memory Map’ (pg. 157), we then find a reference to the section ‘Control Module’ with a given memory range of ‘0x44E1_0000 0x44E1_1FFF’.
Looking at the section ‘9.3 CONTROL_MODULE Registers’ (pg. 758) we then find a list of registers prefixed with ‘conf_’. These are the pad/pin control registers, with a given offset address range of ‘800h–A34h’. All pad/pin mux references in the ‘am335x-bone-common.dtsi’ file are given as offsets from this ‘800h’ base address.
The contents of these pad control registers, i.e. the mux settings, is documented in section ‘9.3.51 conf__ Register (offset = 800h–A34h)’.
Example: Pin mux settings for ‘can1’, using pins ‘uart1_rxd’ and ‘uart1_txd’ as ‘can1_txd’ and ‘can1_rxd’ respectively:
The pin ‘uart1_rxd’ is referred to in section ‘9.3 CONTROL_MODULE Registers’ as ‘conf_uart1_rxd’ and given an address offset from the start of the ‘Control Module’ section (located at 0x44E1_0000) of ‘980h’. Subtracting the pad control register base offset of ‘800h’ from this, we are left with a device tree pin mux reference value for pin ‘uart1_rxd’ of ‘180h’. Using the same process we find a device tree pin mux reference value for pin ‘uart1_txd’ of ‘184h’.
Regarding the mux settings to be placed at the addresses calculated above: looking at ‘Table 9-61. conf__ Register Field Descriptions’ we specifications for many of the #defines given in ‘arch/arm/mach-omap2/mux.h’. Duplicating the settings used for pin uart1_txd (functioning as can1_rxd) in the 3.2 kernel board file ‘board-am335xevm.c’, i.e: (OMAP_MUX_MODE2 | AM33XX_INPUT_EN | AM33XX_PULL_UP) we get:
-
Mux Mode 2: (2 << 0)
-
Input Pull-Up: (1 << 4)
-
Receiver Enabled: (1 << 5)
Adding these together we get 2 + 16 + 32 = 50: 0x32
For pin uart1_rxd (functioning as can1_txd) we then get the setting: 0x12
When this information into the ‘am33xx_pinmux’ section of the ‘am335x_bone-common.dtsi’ device tree file we generate the following:
dcan1_pins: pinmux_dcan1_pins {
pinctrl-single,pins = <
0x180 0x12 /* uart1_rxd.d_can1_txd */
0x184 0x32 /* uart1_txd.d_can1_rxd */
;
};