0b1 is the bitmask (in binary), the same as 0x01 in the "shift and mask"
code I sent. Since the bit you want is already in the least significant
location in a byte, you don't really have to shift it first. You can do
the move and mask with a single AND instruction.
We still have no answer on initial question:
why “set r3, r31.t16” results in r3=0x08 ?
I’d like the pru asm compiler just reject this code as it seems of little sense.
However it does not and produce the instruction coded as 0x1F10FFE3,
Which if deassembled actually is a “SET R3, R31, 0x10”
Then the result of its execution should probably be 0x10000.
Then, why that claimed 0x08 ?? Is it really so?
(deassembly was performed using PRU Opcodes - Pastebin.com)
Yes, I agree. pasm should output the same error message as for
MOV r3, r31.t16
which is
???.p(?) Error: Operand 2 use of .T field not allowed here
There is no error from pasm because this is a valid form of the SET
command (Format 3, Source Abbreviated).
The problem here is that you are reading from R31 using the SET command,
which the PRU reference guide explicitly states does not work. The
reference guide indicates the source will be NULL, which one might
*assume* means all zeros, but in reality could mean just about anything
(including something like "the source input pins on the ALU are floating").
So if you *REALLY* want to know, go ask TI if they'll share details
about what happens when using R31 as a source for the SET/CLR
operations, but I don't think you'll get very far.
----Ursprungligt meddelande----
You are right! I can read any pin with a simply:
LSR r3, r31.b0, 3 //shift and mask
AND r3, r3, 0x01
How can I increment a register eg. r4 bit by bit with the last state of r3 ? what I need is add bits to register.
I tried with SET but without luck.
The PRU has very powerful instructions for bitwise manipulation.
Review the instruction set in the PRU reference guide, or be a bit more
specific about exactly what you're trying to if you want some example
code. Otherwise, I'm not understanding why just adding:
ADD R4, R4, R3
...to the code below doesn't do what you want.
finally I did that with:
LSL r4, r4, 1
OR r4, r4, r3
Hmm… Could you please give us an example which produce bad result?
I widely use the “set reg, r31, bit#” to compose a single bit mask and have never seen any problems.
“Ask TI” is not that good suggestion because they always reply “PRU is not supported” and advise asking questions here.
Thanks.