I’m having an intermittent problem running the BBB’s SPI1 in slave mode. I have designed all my TX messages to end in 0, and have verified every way I know how that the last byte written to MCSPI_TX0 is 0. But after a few minutes of running, there is a non-zero value stuck on the output. It is usually 0x80, (I am in 8-bit mode), and I can clearly see the 0x80 coming out of the D1 line on a scope. The communication is very reliable initially, several messages get through OK before the error. I have to soft reset the BBB’S SPI to clear the error condition.
I’ve been battling this problem for over a month now. I now have a concrete correlation that I can not ignore. The problem occurs when the # of words I write to the TX FIFO exceeds 32 (the internal FIFO size). I looked at the Sitara errata and there is no mention of SPI at all. At his point I would settle for a workaround. I can reset the transmit FIFO after each TX message goes out - is there a way to do this?
Can you check the clock polarity and phase ?
This is always happen in my previous projects
Problem solved. My assumption was that the last value written to the TX FIFO would be the value stuck on the bus if I stopped feeding the FIFO. The TRM (126.96.36.199.2) explicitly says this:
“When the FIFO is enabled, the data read while the underflow flag is set will not be the last word written to the FIFO.”
I assume that “data read” refers to data read by the master. And I never did figure out what the byte stuck on the bus corresponded to, seems fairly arbitrary.
Anyway, the solution is: If using the TX FIFO, you must keep it serviced. If you want to implement a lazy man’s transmitter, that is, only write to the transmitter when you actually have something to send, then don’t use FIFO mode. In this mode it works more like other SPI devices - the byte repeated on the bus will be the last byte written to the TX register.
I am currently doing register programming on the eagle bone blcak. I want to run my BBB as master mode and SINGLE CHANNEL. I have loop backed the pins 18 and 21.
I am sending non-zero data TX0 register and always receiving 00000 on the RX0 register.
Steps that I am following are as follows:
Enabling CM_PER_SPI0 clock
Resetting the SPI module from the SYSCONFIG register
Checking if reset done from the SYSSTATUS register
Writing to SYSCONFIG Register
Write to MODULCTRL register
Write to SYST[SSB] // to set the bits the IRQSTATUS
Enabling the RX0 FULL and TX0_EMPTY from the IRQENABL register
Write to CH(0)_CONF register
Enabling the channel 0 by CH(0)_CTRL register
Now for read/write of 8 bit word
LOOP:(till all the words are transferred)
a) wait till TX0_Empty event occurs
b) put data in the TX0 register
c) wait for the RX_FULL event to occur
d) Read from the RX0 register
e) Reset the status bit of the IRQSTATUS for RX_FULL and TX_EMPTY from the SYST[SSB] = 1
Any help would be great !!!