BBB System Reference Manual Bugs

The SRM contains the following conflicting information:

The System Reference Manual (SRM) says you're supposed to gate all GPIO
(and other inputs) such that they aren't driven until either the SYS_RESET
line goes high (according to SRM section 7.1, 8.0, and possibly others) or
until the VDD_3V3B rail is up (according to SRM 8.6.2). Are these conditions
identical in practice? If not which is the right one?

Also, the reference manual section 8.3.1 says this:

     If you plan to use any of these signals, then on power up, these pins
     should not be driven. If you do, it can affect the boot mode of the
     processor and could keep the processor from booting or working correctly.

while not wrong this paragraph is going to create a dangerous wrong impression
for most readers: that the boot pins are special and are the ones you have to
worry about driving early. I think it would be good to change this paragraph
or add a pointer to the other warnings that apply to all pins or something.

Britton

Those pins control the bootrom's boot selection. If you drive them the
wrong way after sys_reset you can change the processor to boot from an
interface that isn't enable/setup/etc...

Regards,

They are identical actions. Same result. Using reset is easier than waiting on the voltage. The desired action is after voltage. Reset gives you a signal that is easy to use in order to complete the desired function. This is not a “bug”.

This is about DRIVING INTO these pins form external circuitry. It is not about setting up SW to prevent damage from the condition. The processor i sin reset and unable to do anything with the pins until after reset.

There is no DANGER if you do either of these method.

Gerald

Correct. These are the boot pins and will affect the booting process. This is not a damage issue as defined by driving pins to create damage to the processor.

Leave the boot pins alone until after reset is released.

Do not drive the other pins until after 3.3V is up or the Reset signal is released.

Gerald

They are identical actions. Same result. Using reset is easier than waiting
on the voltage. The desired action is after voltage. Reset gives you a
signal that is easy to use in order to complete the desired function. This
is not a "bug".

Sections 7.1 and 8.6.2 give different descriptions of what to wait for
before driving IO pins, without mentioning each other. How is that
not a documentation bug?

This is about DRIVING INTO these pins form external circuitry. It is not
about setting up SW to prevent damage from the condition. The processor i
sin reset and unable to do anything with the pins until after reset.

There is no DANGER if you do either of these method.

Ok, thanks. One related question: I have a switch debounce IC
(MAX6818) powered from the 3V3 rail. Assuming its outputs rise
together with its power, will the connected bone inputs probably be
ok, or is it necessary to wait for 3V3 to be all the way up to be
safe?

Britton

Ah, I understand. They can't be driven during boot. I was stuck on
the power issue.
It might be good to change section 8.3.1 to this:

     If you plan to use any of these signals, then during boot, these pins

^^^^^^^^^^^
     should not be driven. If you do, it can affect the boot mode of the
     processor and could keep the processor from booting or working correctly.

"on power-up" changes to "during boot" or something.

Britton

OK. I will fix them in the next version and state that both are options in each of those locations to prevent the issue from occurring… That should take care of the bug.

.As you can see from the schematic, the I/O rails are powered by 3V3A. Expansion rail is 3V3B which is enabled by 3V3A, so this should not be any issues if you do what you are saying you are doing…

Gerald

Yes, I was as well. They are separate issues. This is where the reset comes in for sure. Hold off driving these pins or adding a load to the pins until after RESET goes high. This insures that they are not driven or loaded during the period in which they are being read by the processor to determine the boot mode.