[beagleboard] Beta Testers - FPGA shield for Beaglebone

looked around the site. still couldn’t see how you intend to interface to the beagle board and which beagleboard you intend to target. Got a link to cover that, maybe I missed that info somewhere. Ideally an fpga board would be mapped into memory and/or io space for fast transfers and maximum integration with the beagle.

Eric

See the title - it's for the Bone!

Leon

looked around the site. still couldn’t see how you intend to interface
to the beagle board and which beagleboard you intend to target. Got a
link to cover that, maybe I missed that info somewhere. Ideally an fpga
board would be mapped into memory and/or io space for fast transfers and
maximum integration with the beagle.

See the title - it’s for the Bone!

Leon

Leon Heller
G1HSM

Didn’t see any details on how you intend to interface to the bone. hoping the interface to the bone is signifigantly different than the interface to the arduino as the bone is much more capable.

Eric

As an update. I changed up the interface to make it a direct plug in for the BB. I also updated the schematics so that anyone interested can see the specific wiring from the BB to the FPGA. See the project site for specifics. Let me know if you have further thoughts.

I just saw the new Arduino Due: http://www.wired.com/design/2012/10/arduino-due/
Even more pins to connect!

By this stage, I would suggest “splitting” your design: if you still want to support all the Arduino baseboards, consider a series of adaptor boards rather than a single direct plug-in. You could move some of the buttons, switches, even PMODS to the adaptor boards, sell them seperately, and discount the main board. Sales will show which boards are your biggest market.
Mind you, with an ARM M3 your board, as it stands, could probably give the “real” Due a run for its money.

Sorry if I sound picky. Part of my job (Lockheed Martin) involves reviewing draft proposals from the local engineers. A picky review at the start can save dollars and headaches in the long run (or so they tell me).
That’s also why I promote the high-speed ADCs with LVDS outputs. I know of a few engineers who’d really like an FPGA kit with good data acquisition (better than PMOD currently offers) for DSP design.

In fact, if I was to push my own agenda, I’d suggest you leave space for an SI-570 programmable oscillator. Combined with the ADCs you get 80% of SDR hardware, leaving only an analog front end.

Regards,

– Alan Campbell