BeagleBoard rev. c4 + Composer Code Studio 5.3.0 + XDS100v3

Hi everybody

Anyone are experienced with topic subject?

When connect ARM:

Cortex_A8_0: GEL Output: OMAP 32K Watchdog Timer is disable
Cortex_A8_0: GEL Output: Putting DPLL into bypass before proceeding
Cortex_A8_0: GEL Output: Putting CORE DPLL into bypass before proceeding
Cortex_A8_0: GEL Output: Locking CORE DPLL
Cortex_A8_0: GEL Output: PRCM clock configuration IIA setup has been completed
Cortex_A8_0: GEL Output: SystemClock = 19.2 MHz
Cortex_A8_0: GEL Output: DPLL_MULT_VALUE = 242
Cortex_A8_0: GEL Output: DPLL_DIV_VALUE = 13
Cortex_A8_0: GEL Output: CORE_DPLL_CLK = 663.771 MHz
Cortex_A8_0: GEL Output: CORE_CLK = 331.8855 MHz
Cortex_A8_0: GEL Output: L3_CLK = 165.9427 MHz
Cortex_A8_0: GEL Output: MM02: mDDR Micron MT46HM32LFCM - 512 Mbit(64MB) on CS0, 4M x 32bit x 4Banks
Cortex_A8_0: GEL: Error while executing OnTargetConnect(): Target failed to read memory at 0x6C000010 at (*(SMS_SYSCONFIG_REG)|=(2<<3)) [omap3430_sdrc_configs.gel:394] at common_sdram_init(1, 0, 2) [omap3430_sdrc_configs.gel:242] at mDDR_Micron_MT46HM32LFCM() [omap3530_cortexA.gel:222] at OnTargetConnect() .

When connect C64XP:

C64XP_0: Error connecting to the target: (Error -1178 @ 0x6D) Device functional clock appears to be off. Power-cycle the board. If error persists, confirm configuration and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.0.872.0)

Please help me anybody!

Thx.

Which board is this?

Gerald