I am just curious but what is that maximum practical amount of data
the beagle board can read through the SPI buss?
I need to read around a sustained 384 K bits a second. It is a data
logging application and I am planning on buffering the data so real
time will not be required but I will have to average that high of a
though put to use the spi buss.
Theoretical maximum data rate through one of the SPI ports is 48Mbps -
that's the highest clock rate the TRM specifies. In practice you'll
see less than this due to internal DMA bottlenecks in the OMAP. In
some simple tests that I did using an 'almost stock' OE kernel, I saw
some throttling when the SPI clock rate was in the 20MHz range. Some
have suggested that this could be corrected by optimizing the internal
data path allocations, but I've got no idea where you'd start with
In any case, I'd guess you wouldn't have any trouble hitting 384kbps
with SPI 'out-of-the-box'.
We use the SPI on the Beagle board at 1mb/s connected to a daughterboard with a FPGA. We push it at 5 mb/s and it was ok.
So it normally works at 384kb/s
However the SPI port is connected to the L4 bus, like the MMC card and some other peripheric. So it’s also depend of the use of these peripherics and activity on the L4 bus.
2010/4/19 emeb <email@example.com>