The DM3730 supports a slight increase of L3 bus and memory clock rate
from 166 to 200 MHz relative to the OMAP3530. Is it possible to use
the 200 MHz rate on the BeagleBoard-xM? The SRM mentions both speeds
(on pages 22 and 23); when booting the Angstrom 2.6.32 kernel I see
the following messages.
[ 11.166534] Unable to set L3 frequency (400000000)
[ 11.171447] Switched to new clocking rate (Crystal/Core/MPU):
26.0/332/1000 MHz
[ 11.178863] IVA2 clocking rate: 800 MHz
These seem to indicate that the maximum DSP and ARM core clock rates
are being engaged, but not the L3 interconnect. Is this a hardware
limitation (i.e. memory chips) or a kernel limitation?
The message is printed at [1] , but I believe the SDRAM is already
running at 200MHz clock rate when U-boot/Kernel is loaded, as X-loader
initializes SDRC registers [2] ?
Thanks Joel. My concern is that the kernel is clocking the L3 bus
down to 166 MHz, even if X-Loader may have set it to 200 MHz at
startup. When I check the CM_CLKSEL1_PLL register using devmem2, it
reads 0x094C0C00, which seems to indicate that the current speed is
166 MHz. Is the memory chip on the BeagleBoard-xM (I have Rev C with
Micron memory) capable of 200 MHz operation?
If I remember correctly, if you run the processor at 1GHz, the L3 needs to be slower in order for the math to work out. Run it slower and you can increase the L3 speed.
If I remember correctly, if you run the processor at 1GHz, the L3 needs to
be slower in order for the math to work out. Run it slower and you can
increase the L3 speed.
I'm running mine (rev B) at 1GHz CPU and 200MHz L3 with no apparent
adverse effects. I'm using a couple patches to x-loader and kernel to
achieve this. Fixing these up to detect the board and apply the correct
settings is left as an exercise.