You can also fix most strapping options, including the PHY address, by writing to mdio register 0x12 (see datasheet page 60).
This whole issue still sounds really weird though. The RXD3/PHYAD2 line has internal pull-down in the PHY, internal pull-down in the AM335x, and external pull-down. How on earth can the PHY manage to sample it high?
This also makes no sense:
I guess the problem was, as described in the reply from Texas Instruments mentioned by Micka (I misunderstood that earlier), that LAN8710A starts to function correctly at a slightly higher voltage level than the microprocessor, and may come out of reset too late with respect to the microprocessor. This agrees with the observation that a higher capacity on nRESET_INOUT only worsens things, because it makes the slope of the reset pulse more flat, thus increasing the time lag between the starts of the two chips.
The PHY latches its strapping options (except REGOFF) at reset deassertion (rising edge of nRESET). It has a minimum time (but no maximum) between power supplies valid and reset deassertion, so if it were true that it considers its supplies to be valid rather late then a longer reset time would be required, not a shorter one…
I have another interesting case to add to the list: I found my BBB unreachable via network. It had network on boot, but about three days later I noticed it was unreachable. On closer inspection I observed that its link led was inverted: with cable disconnected it was on, after connecting cable it blinked briefly and then turned off. Its speed led was continuously on, hence probably also inverted. The device it was connected to correctly detected link up/down on cable connect/disconnect, but reported that auto-negotiation was not supported by link partner and ended up selecting 10base-T half-duplex.
The BBB itself had just a single link down message in its log and did not notice the reconnections at all. “mii-tool -v -v” produced garbage: it showed all registers as fffb, which I discovered is its way of saying “can’t communicate with phy”. (I get the same output if I change the phy’s address via register 0x12. Incidentally, this also produces a “link down” and the cpsw driver does not recover if I change the address back… not very resilient.)
The inverted link led is really weird though: according to the phy datasheet it corresponds to the REGOFF strapping option, which (unlike all other options) is only sampled at power-on and disables the internal 1.2V core voltage regulator. However, I measured PHY_VDDCR and it was in fact at 1.2V, and after a reset the phy functioned normally again, no power cycle was needed. Very very strange.
I do hope that on the x15 the phy reset(s) will be on GPIO? (Also to avoid pointlessly resetting them when rebooting, which is especially undesirable when using the integrated switch.)
It does sound like folks have fixes in the works though.