beaglebone gpio source interrupt latency. adc sampling.

Greeting everyone.

I would like to now what is the maximum sampling frequency one could achieve from an external 16bit-adc connected to the beaglebone(white or black). Using linux.

Consider the following scenario. The adc conversion is triggered by a pwm, when the conversion is done the adc is latching the results to the output bus and raises a pin.

  1. The best interrupt responce time i could achieve using through a kernel module was flactuating around 6us.Is there a way to improve that?
    Do we have achieved something better?

  2. I have thought going around it by setting a edma transfer triggered by an external dma request. i have thought that this should be a lot faster as it shouldnt involve the kernel at all. Is this a valid thought?

  3. If the source address of the edma transfer is a gpmc address would edma and gpmc work together?
    Imagine the following scenario: the adc creates an external dma request ,the edma responds , gpmc reads the bus , edma transfers the data to the memory. Is this a valid scenario?

Greeting everyone.

I would like to now what is the maximum sampling frequency one could
achieve from an external 16bit-adc connected to the beaglebone(white or
black). *Using linux.*
*
*Consider the following scenario. The adc conversion is triggered by a pwm,
when the conversion is done the adc is latching the results to the output
bus and raises a pin.

1) The best interrupt responce time i could achieve using through a kernel
module was flactuating around 6us.Is there a way to improve that?
Do we have achieved something better?

The PRU has I/O specifically designed to do exactly what you want, latch
a set of pin values when one signal changes value (ie: rising or falling
edge). See section 5.2.2.3.2 "16-Bit Parallel Capture" in the PRU-ICSS
Reference guide.

2) I have thought going around it by setting a edma transfer triggered by
an external dma request. i have thought that this should be a lot faster as
it shouldnt involve the kernel at all. Is this a valid thought?

It might be. I haven't played with the DMA engines on the AM335x enough
to know what you can and can't do.

3) If the source address of the edma transfer is a gpmc address would edma
and gpmc work together?
Imagine the following scenario: the adc creates an external dma request
,the edma responds , gpmc reads the bus , edma transfers the data to the
memory. Is this a valid scenario?

According to section 10 "Interconnects" of the TRM, the TPTC (Third
Party Transfer Controller, a.k.a. DMA controller) is connected to the
GPMC, so this should work if you can get the request part sorted out.

If you're using the GPMC interface, you'll also have to either play nice
with the on-board eMMC memory or disable it and keep it reset.

Thanks a lot for your input Mr Charles Steinkuehler
Especially for the PRU that could be a good alternative for some adcs.
I am working my way through the dma registers atm to do some first tests.
I will post updates whenever i can.

If anything else crosses your mind please inform me.

Many thanks