beaglebone halt when pin P8-39 and pin P8-41 connected together

Hi, All

I am recently working with my beaglebone Rev. A3 hardware stuff. I
found beagleboard can not boot up on a new power cycle, if I short
circuit P8-39 pin and P8-41 pin on header P8.

The signal name of those 2 pins involved should be lcd_data6 and
lcd_data4, per beaglebone SRM. Similar symptoms could be observed, if
I connect P8-39 and P8-41 together.

Anyone give some explaination on that, or anyone has same issue? We
have a new beaglebone cap designed but could not boot up correctly by
this issue.

Regards

Check the schematics, I bet those pins are also used for SYS_BOOT and have different levels...

-- Bas

Hi, Bas

Thanks for your quickly response. I have a serach in schematics and
find lcd_data0-lcd_data15 are all multiplex pins for boot mode
selection.

Is there any logic isolation design available, to make our
customerized hardware living with this AM335x boot mode mechanism? I
mean customerized hardware with strong pullup or pulldown on lcd_data0-
lcd_data15 pins.

Thanks again for your help on that.
Regards

Hi, Bas

Thanks for your quickly response. I have a serach in schematics and
find lcd_data0-lcd_data15 are all multiplex pins for boot mode
selection.

Is there any logic isolation design available, to make our
customerized hardware living with this AM335x boot mode mechanism? I
mean customerized hardware with strong pullup or pulldown on lcd_data0-
lcd_data15 pins.

Thanks again for your help on that.
Regards

Here are some possible solutions:

- Choose your signals wisely, i.e. make sure the level of your strong
pullup/pulldown corresponds with the boot mode.
- If you're driving a pin (input), make the driver a tri-state buffer
with an enable that you activate only after boot.
- If you're using a pin as output and need the opposite default level
(pullup/pulldown), add an inverter and keep the bootmode default.

Note: Not all levels are mandatory, sometimes the device will still boot
but slower and maybe checking other devices first. However if you change
the levels defining the clock you're out of luck...

-- Bas

Make sure nothing drivers these pins until AFTER the reset line has gone high and an additional delay for around 1 sec after that point. I would use another GPIO pin to activate your circuitry via the SW.

Gerald

2012/3/4 Bas Laarhoven <sjml@xs4all.nl>

Thanks Gerald and Bas,

We prefer a pure hardware solution like a latch signal from am335x
boot module for switch between.
We have to have a monostable logic there if this latch signal
unavailable from am335x.

Regards

You could also use a reset IC that is triggered by the reset line to add a deterministic amount.

Gerald

2012/3/4 beada <service.esky.sh@gmail.com>

You could also use a reset IC that is triggered by the reset line to add a deterministic amount.

Gerald

Or you can, if not all GPIO are taken, use one or two pins of these to switch state.
Because I wasn’t sure about the power-up state of the processor I used two pins that would power-up identically, after configuring these as outputs, one needs to be set low and the other must be set high to enable the drivers that conflict with the SYS_BOOT pins. This only takes a single FET and a resistor and may be the cheapest way to do this. Seems to be working fine.

– Bas

how to identify the RGB data pins in the AM3359 processor… 8 red datas 8 blue datas 8 green datas. Totally 24 pins