Beaglebone McASP clock signals


I want to capture audio data from a 4-channel ADC (not the AIC34) via McASP0. I want the beaglebone to be the clock-slave, so frame-sync (AFSR) and bitclock (ACLKR) are provided by the ADC. What I don’t quite get is the role of the McASP’s high frequency clock pin (AHCLKR).
If I use a 4-slot TDM, a slot-width of 32 bit and a sampling frequency of 48 kHz the bitclock-frequency is 6,144 MHz. What what be the frequency of the high-frequency clock (AHCLKR) and why is it needed anyway (can it be bypassed?)

Any comments are appreciated!