BeagleBone UART Serial 2,3,4,5

Hi, anyone know how to use the UARTS 2 ,3,4 and 5 for the beaglebone?
For the uart 1 , just need to change the mode from OMAP_MUX_MODE7 to
OMAP_MUX_MODE0 with the script in this link

But on /sys/kernel/debug/omap_mux/ there is only mux
configuration for uart 1 but not for 2,3,4and5

root@beaglebone:~# cat /sys/kernel/debug/omap_mux/uart1_txd

name: uart1_txd.(null) (0x44e10984/0x984 = 0x0037), b NA, t NA
signals: uart1_txd | mmc2_sdwp | d_can1_rx | NA | NA | NA | NA | NA
The mux is in mode 7 (NA) instead of mode 0 (uart1_txd) by default.

Any help is welcome


Although I haven't tried using UARTs other than UART1, I can tell you
where there mux settings are.

The /sys/kernel/debug/omapmux filenames are taken from the Mode 0
usages of the pins, regardless of which mode the pin mux is currently

You can get the mode 0 names from Tables 10 and 12 of the Beaglebone
System Reference Manual.

For example, uart2_rxd is in Table 12 of the SRM (port 9 pin 22), and
the mode 0 usage for that pin is spi0_sclk. So, the mux setting uses
the following file:

root@beaglebone:/sys/kernel/debug/omap_mux# cat spi0_sclk
name: spi0_sclk.(null) (0x44e10950/0x950 = 0x0037), b NA, t NA
signals: spi0_sclk | NA | NA | NA | NA | NA | NA | NA

In this case, it is currently in mode 7. Since uart2_rxd is mode 1,
you would change the mode (and keep the receive bit enabled, but set
the pullup to pulldown) with:

root@beaglebone:/sys/kernel/debug/omap_mux# echo 21 > spi0_sclk
root@beaglebone:/sys/kernel/debug/omap_mux# cat spi0_sclk
name: spi0_sclk.(null) (0x44e10950/0x950 = 0x0021), b NA, t NA
signals: spi0_sclk | NA | NA | NA | NA | NA | NA | NA

As I said, I haven't actually tried using UART2, so I can't say for
sure that this mux setting works as expected.


Hi, tanks a lot u give me a great help. Based on that help and on the
first script for UART1
I just replaced the values

uart1_pin_mux = [
('uart1_rxd', (0 | DDR_IN)),
        ('uart1_txd', (0)),

for this ones

uart2_pin_mux = [
        ('spi0_sclk', (1 | DDR_IN)),
        ('spi0_d0', (1)),

For the ones with same problem the entire python script is here

import os
import logging
DDR_IN = (1 << 5)
DDR_OUT = (0 << 5)
PULL_R_UP = (1 << 4)
PULL_R_DOWN = (0 << 4)
PULL_R_EN = (1 << 3)
PULL_R_DIS = (0 << 3)
uart2_pin_mux = [
        ('spi0_sclk', (1 | DDR_IN)),
        ('spi0_d0', (1)),
for (fname, mode) in uart2_pin_mux:
        logging.debug("%s = %s" % (fname, mode))
        with open(os.path.join('/sys/kernel/debug/omap_mux',
fname),'wb') as f:
                f.write("%X" % mode)


tried in uart 1,2,4,5.
Its working. Edit the board-am335xevm.c and mux33xx.c
and call the init in beaglebone a3 revision

it will work

Hi, does anyone had trouble using UART1 and UART2? Why am I making the correct settings, but the rx of the UART1 stopped working. Can Anyone helpe me?

Hi, Nikhil, Can you help me? When I set up the UART2 and try to use a code to communicate between UART1 and Uart2, the uart1_rxd stops working but uart1_txd still works. Can you explain why?


TI didn’t map all pins in the mux table properly. That’s the reason why you see uart1_txd.(null) since this pin is mapped to mux mode 7.
You can update the mux table am33xx_muxmodes[] in kernel/arch/arm/mach-omap2/mux33xx.c file. In this file, the current entry for UART1_TXD as followings:

“uart1_txd”, “mm2_sdwp”, NULL, NULL,

It should be mapped with all possible combinations :

“uart1_txd”, “mm2_sdwp”, “dcan1_rx”, “i2c1_scl”,
“pr1_uart0_txd”, “pr1_pru0_pru_r31_16”, “gpio0_15”),

In OMAP_MUX_MODE7, the name will be uart1_txd.gpio0_15. If you want to use uart1_txd (mode 0), you should change the mux mode to OMAP_MUX_MODE0.

Check out the file board-am335xevm.c to change mux mode for the pin that you need