REPORT - WEEK 8
Hello Everyone,
Wow ! 8th week report ! Time is moving pretty fast … !
Anyway, this time, I am not going to make any comment about the last week. Would just say that I really need to work hard … harder than I am already working.
Last week :
Tasks for last week were:
- Completing the driver.
- Starting discussion on the interface for the parallel_bus driver.
- Time reserved for improvements in the fw.
1. Completing the driver:
Till now, I have been able to get the driver probed whenever a rpmsg-channel named ‘beaglescope’ gets created. Now since this driver will contain all the iio_device_driver code and the rpmsg_client driver code, I think there should be two ways to get this driver probed. One when the rpmsg_channel named ‘beaglescope’ get created (this has already been implemented) and the other when the adc is plugged in.
I read other ADC driver codes and found that they register the device name to their associated bus, and that bus driver then probes the device driver.
In our case, there can be two ways to implement this :
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Using a device tree overlay. I am already somewhat familiar with this device tree overlay. But if we use this approach, we will have to specify the gpios and their mux settings to route them to the associated PRU-pins. This will probably result in a conflict with the universal cape that is already present and loaded onto the newer kernel images.
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Use the EEPROM present on the board and use BBB’s I2C bus to probe the driver. This approach seems more interesting to me, as its like plug and play, and it is what other iio_device_drivers do. So can this be done by registering device name to the I2C bus driver ? I am not sure how this works internally. Does the I2C bus keeps on checking reading on its I/O pins every time ? Or it uses some other mechanism to do this ?
As far as the current state of the driver is concerned, it actually took me time to understand the IIO data structures and how to relate it with the ADC device that I have. I have got some understanding but its still not completely clear to me. I had some doubt and Michael helped me with it. I will keep asking as I move along.
As of now, The driver gets probed, registers itself to the IIO subsystem and the iio sysfs bindings do appear according the channel specifications (https://gist.github.com/ZeekHuge/c0334c14d33ce62d6d27552a18073b01). I am working to add the read raw methods to the driver. I have already added the read_raw methods actually, but it isnt working and was getting late to write the report so I left it there.
2. Starting discussion on the interface for the parallel_bus driver :
Ahhh … well, I haven’t officially started to discuss about the parallel_bus driver, but I have started to gain understanding about how to go along.
Okay so what I am getting out of all the work I have done till now is :
Virtio framework is used to create virtual devices and buses. So the virtio_rpmsg_bus is actually a virtual bus over which data is transfered. Now the rpmsg client driver uses a structure called rpmsg_channel. This rpmsg_channel (aka rpmsg device) is a virtual device that is connected on the vitio_rpmsg_bus (a virtual bus). So a client driver actually communicates to this, rpmsg_channel device , which further communicates to the pru over the virtio_rpmsg_bus.
Now for our purpose, the parallel bus driver that we need to develop has to be like virtio_rpmsg_bus, and it shouldn’t be like a rpmsg client driver, which would just communicate to the rpmsg_device. I think this will be unnecessary overhead and not the right approach.
So with the limited knowledge I have, I think we will have to do some modifications ( probably minor ones ) in the virtio_rpmsg_bus driver to finally make it a pru_parallel driver. This would also provide us with the opportunity to increase the size of the buffers, that is limited to 512 byte in virtio_rpmsg_bus.
Though we can do it later and go on with the rpmsg_client approach to implement the pru_parallel driver for now.
Please let me know your thoughts on this.
3. Time reserved for improvements in the fw.
Okay so the fw had some limitations. The most imp one was about its duty cycle, as also mentioned here ( https://github.com/ZeekHuge/BeagleScope/issues/1 ).
So I have removed the redundant code form the fw source and some of the unused DELAY macros, and have added another DELAY macro that would replace the one already being used.
The new macro is : THE_DELAY
macro already being used : DELAY_SAMPLE
(please refer to the code (https://github.com/ZeekHuge/BeagleScope/blob/port_to_4.4.12-ti-r31%2B/firmware/main_pru1_def.asm) if the explanation below seems out of context )
The least delay that we can have using DELAY_SAMPLE is of 2 cycles, but with THE_DELAY macro, its of 1 cycle.
Now, The plan is to include this THE_DELAY macro in the TAKE_SAMPLE_8 macro like this :
CLK_TOGGLE
THE_DELAY
MOV RX, R31
THE_DELAY
CLK_TOGGLE
Further, all the occurrences of DELAY_SAMPLE macro will be replaced by the THE_DEALY macro. This will result in a completely configurable clock duty cycle, without any loss in the max configurable sampling rate that can be achieved (this code will be able to sample at about 28MHz )
I tried to add these changes, but the code wont compile as it becomes large to fit into the code memory. I went back to the PRU manual and found this MVIx instruction. I tried to use it, but the instruction is a bit ‘awkward’ as it works sometime, and do not work other time. I am working to understand how to use it. Using this instruction will probably decrease the size of SAMPLE_CYCLE_8 macro, atleast that is the plan, and then we will be able to use THE_DELAY macro.
I have also added two modes of sampling.
RAW_READ : this reads one single sample, instantaneously and sends this 32 bit sampled data back to the kernel just once.
BLOCK_READ : This is what the PRU was already doing, sampling data continuously, until its interrupted and sending it back to the kernel in blocks of 44 bytes at a time.
To introduce all these modes and the configuration related to clock duty cycle, it was required to increase the size of configuration data that the kernel sends to the PRU. Earlier, it was just 232 bits, now its increased to 332bits
- BONUS 
Please see this : http://www.zeekhuge.me/post/some_shots/
I worked out to get the hardware setup. I couldn’t get the standard things from the local shop, so I made them myself.
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The new BBB pins were fried up, due to wrong resistor values. I got old one from my college. Had a 2A ,6V power source (it was rated 5V but was giving 6V and BBB wasn’t booting up), so used a voltage regulator to convert it to 5V.
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I have never seen such power pins, as where there on the ADC. What I just did is, soldered them to a wire with female connectors on the other side.
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ADC needs to be kept safe (Though I love blowing things up
). So I have got a variable voltage regulator as ADC’s power source and I will use it at 2.5V ( and will increase only if ADC needs ) to be on the safe side.
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I have got this arrangement of male header pins on a perf boarrd, at positions where the PRU pins are routed out, and it fits nicely on the BBB.
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Finally, there is that female connector, to connect to the ADC output pins.
Getting all this done took me 2 days. And then I returned back to the software. I will do same the next week, but I wont give it more than 2 days.
Next Week:
Tasks for the next week:
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Completing the drive.
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Starting discussion on the interface for the parallel_bus driver.
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Time reserved for improvements in the fw.
Thats all for this report.
Thank you