Been working on a beaglebone-fpga cape. First public show of design files

Good Evening Beagleboard community,

I would like to share with everyone my beaglebone-fpga cape that I have been working on for the past 4 or 5 months. It started with a question on the forums about interfacing an fpga to the beaglebone:!searchin/beagleboard/fpga/beagleboard/sGEZX0r3AxY/iBlY0Wj3vcYJ. I had already been thinking a little about this, and started doing my own homework on the subject. The links provided by Jonathan Smith proved valuable to get an idea of what is capable. I saw that Special Computing was doing a board like this, but with a Spartan 3. ( Unfortunately, there hasn’t been an update since last year. There are a few other fpga – beagle* projects out there:,!topic/pandaboard/UiaTB6AiQeM, and the beaglebro for the *bone (or something similar, I can’t find the link, but remember the project was on hold). None of these were something I could get my hands on for the beaglebone, and start messing around with it. So, I set out to make my own.

I choose a Xilinx Spartan 6 XC6SLX25-2FTG256C because it was the largest Xilinx fpga with 1 mm pitch. I went with Xilinx because I already have a Spartan 3 and am more familiar with Xilinx than anyone else. I have used Jacek Radzikowski’s beaglebone template (!searchin/beagleboard/beaglebone$20flyingbone/beagleboard/eqdgCb8PllQ/3a0vTyGxIGMJ and dude if your reading this, you rock for making it!). The power supplies I chose LTC 3546’s since the Digilent Atlas board uses them. (why reinvent the wheel right?). The beaglebone to fpga connections are I2C, SPI, an interrupt line, and the GPMC. Initially I wasn’t going to length match the GPMC lines. I didn’t think it would matter too much for my purposes, but then I got thinking about experimenting with accelerators on the fpga, so yeah, it would matter. With the information provided by Gerald (!searchin/beagleboard/fpga/beagleboard/YvmYKZgdjps/0LxcepOuQf8J, thank you again for your help. It definitely saved me a couple nights. Took so long since I ended up changing a few of the pins to make it fit nicely.) I have redone my board to have the greatest difference in length to be 9.1 mm, with an FR4 material the delay should be less than 4 ns. This is what I believe the greatest delay across any of the data lines to be, all the other are less, and with the GPMC’s minimum select able time of 10 ns I think this is ok. The CSN, ADVN, BEON, OEN, WEN, and BE1N are not length matched. From my understanding of the TRM, I can program each of these timings individually, so I hope to compensate that way. If it doesn’t work, I’ll fix it in my next board spin. (I have a short list of things to change for board 2 already, but have to see how gen 1 does first!).

That’s enough of background I think. Here are my design files: . These are still my first crack, and gerbers aren’t up yet. I have 5 DRC errors to fix, but I wanted to get my design out there for critique. I think it (and myself) are ready for that! Now, I know that my stack up is not the best, and some of the routing is a bit sloppy, but it is my first board, and the guys who I have gotten to look at it so far haven’t completely torn it up in a while (They have a few times already… I was really bad a routing at first). They have actually said that it will probably work (not ideal, but should work). I will be fixing those few errors tomorrow, and will upload the gerbers. The gen 2 board will fix much of the amateurish nature of this board. Eventually, I will do a more thorough write up of my design choices and thinking. Also, I’m fairly new at git, so if something is missing or wrong, please let me know!

I’m hoping to get any feed back from the community of my hardware design, and ideas or tips for software development. My game plan for software is to first verify the FPGA works by toggling the control lines on the on the board I2C IO-Expander, and then program a simple bit stream over the SPI bus to flash the on board leds. Later, I want to start playing with the GPMC (like this guy has: Long term I want to write a kernel module to handle the *bone-fpga communication and start messing around with the concept of “Peripherals on Demand” like the Armadeus Project (

I’m hoping that this work interests the community. I plan on using it as the base for my final capstone project, so will hopefully push it along fairly aggressively. Right now I’m not sure what license (if any) to release this under, so if any one has any feedback on that, I’d love to hear it. Right now, I would just like that my name be somewhere associated with it. I’d love to work with someone(s) to make this something worthy of adding to the official capes list some day! (But I feel that that is at least half a year and another board away).

I plan is to send to manufacturing by the end of this week. (I’ve told myself that before, but I mean it this time!). If you see any critical, “THIS WILL MAKE IT NOT WORK!!!” type mistakes please let me know before Friday. After that, I keep my fingers crossed until the board returns some time mid september.

Thanks everyone, and good night!

I'm glad you found it helpful. I've already lost hope anybody will
ever use it :slight_smile:



I’m stilling working on the board. Getting a manufacturer was more difficult than I expected. I have now found one that is helping me bring up a prototype. The initial cost was pretty high for prototype boards, but they have sent me a list of things to change to reduce the cost. I’m currently making those changes and expect to be finished by the weekend. Then, I’ll be resubmitting, and hopefully having working boards soon. This has been an excellent lesson in hardware design taking (much) longer than initially expected.

The design files are all made in Kicad. I can see about posting pdf’s latter on, but right now I’m making changes every night or so, so I’d rather hold off until they are done and sent for production. Feel free to grab everything from my github, and message me if you want anything else, or spot something funny in any of the files.

Once I have a few units in hand, and tested that they work, I’ll gladly send them off to people to play with at cost + shipping. The software / softcores are what will probably take the most amount of time, and more people working on that, the faster it is useful for me too :stuck_out_tongue:

This first prototype run is for very few units, looking at 5 or so. If people are seriously interested, I don’t mind going for a larger production run.

I’m glad to see that there is still interest in this board. I’m not the best for keeping people updated, but I am still working on it!

Have a good one,



once the board actually works I think cores will be the easy part. I think a big part of the market for such a board is those who would like to use it to learn Verilog/VHDL. the chosen part I believe is supported by Xylinx free software dev tools. Simply having an FPGA on the bone that one can download code to from the bone is by itself huge as a learning platform. past that, I can see a community around such a cape alone building larger more capable cores and so forth. I’ll also mention that there are sites and communities such as that have freely available cores.

Also, hopefully you’re keeping a development log on this project. It would be interesting at some point to see the design process and what kind of changes went back and forth to reduce cost (and maybe have them open for people to look at weighing if lowest cost is always the best option).


Aah - OK, I’ve loaded up Kicad at home and I can see you’ve put a LOT of work into this board. Big BGA designs are scary - I probably would have settled for the LX9 in the 144-pin flatpack (or pinched some board layout hints from the Avnet microboard).

Can I ask: which layout is the latest?

I’m looking at bonefpga.brd (it seems the most complete) but layer “Inner4” is very confusing. Under the FPGA, you have an Area Fill that seems to connect pin A9 (GND) with D12/E12 (VCC_O).
It also connects to F11/G10 (3.3V) and a few others. I hate to think about shorted power supplies in a 6-layer board, so I hope I’m wrong.



If you say so :stuck_out_tongue: My knowledge about fpga cores is less than that of hardware design (not that hardware design is very much at this point). It would probably take me longer to get those aspects going, but I have a rough plan and outline on how I want to go about it. This could be a pretty cool add-on, with a lot of neat projects. I’ve also become really interested in the whole hardware/software co-design idea, and the things that the Armadeus Project have done. This could be a cool platform to do those sorts of experiments. I’ll check out opencores. Maybe there is something I can use. For now though, I’m pouring all my time to getting this out the door :slight_smile:

I’m not the best at documentation… I have been meaning to write up a hardware architecture document outlining all my design choices and process. Right now, it’s all mental. No body has been driving me to do it but I know I have to, and it’s been nagging at me. Eventually, I will write everything up. I’ve also been thinking about starting a blog to document all this. It would be more fun than writing word documents, so it wouldn’t feel like documentation, so I would (in theory) do it. Sorry I can’t give a more positive response about this.


In hind sight, I probably should have. My thoughts were that since I had used a Spartan 3-200k to nearly full capacity in one of my projects, that I would go with the largest Spartan 6 I could get my hands on at a reasonable cost, and not at some ridiculously small pitch. The largest with 1mm ended up being this one. When I did the layout the first time I had no idea about proper BGA fan out. I have since found Xilinx’s app notes about fan out, and the manufacturer I’m working with sent me a pdf with guide lines and recommendations.

The “bonefpga.brd” is the latest. The others were failed first attempts at getting the GPMC lines right. With the current design, I’m pretty happy with those. They are length matched for the Revision 3 beaglebone (It’s the one I have). On a later spin (if the interest is there) I don’t mind changing the lengths to match the most common beaglebone’s lengths, but that’s months away.

I see what you mean around A9. That via is blind connecting the Back to Inner2, so I think it would have been ok. The manufacturer actually highlighted the area under the fpga as a potential problem area, and I’m redesigning it (Now that I have found bga routing guidelines from Xilinx). The biggie is that I need to remove all blind vias. This will hugely reduce the cost.

One of the things I should explain is my thinking with all the power islands, and the 4 voltage rails. Initially, I had thought to have the 2 interface banks from the fpga to have select-able voltage using Jumpers J701 and J702. When I started out I thought I might want to play around with interfacing to LVDS devices, and didn’t want to muck around with level translators. I’m now redesigning away from that. It ended up too complex and made the inner layers really ugly. Right now I’m going with 3 rails, 1.2 Vint, 3.3 Vaux, and 3.3 Vcc_x, using a design created using TI’s (National’s) Webench software. I’ll post the pdf of that later today.

The other bit of weirdness with those is that I originally did the regulator layout based on the fpga being in a slightly different place, and rotated 90 degrees clockwise from how it currently is. In that conformation, all the regulator outputs and the islands they were to feed were very cleanly lined up… The position and rotation was done to better fit the GPMC lines. Initially, the GPMC lines were going to connect to the fpga’s parallel configuration lines. I had wanted to play around with parallel and serial bit stream loading. After trying to route the lines many times, I gave up, and rotated the fpga to connect the GPMC to this bank that had enough pins along the edge to make routing much easier. With this configuration, I was able to length match the lines.

This board is probably an order or 2 of magnitude more difficult than any other I have done. My last was simply a switching regulator. All in all, it’s come together fairly nicely (minus the problem areas). I’m still working through the manufacturer’s recommendations, and think I’m on target for finishing by Friday.

If you spot anything else, please let me know.

Have a good one,


Hello Everyone,

I’ve made a few changes to the design, if you guys want to take a look at it:

My midterms are now over for the most part, so I’m back at developing this cape. I put my thoughts for each of the changes in the README on github. If anyone wants more info on what I was thinking, please don’t hesitate to ask!

I wish I could give a time from for everything being finished, but as the last few weeks have shown, I’m not so good at predicting how long things take when other things come up (midterms, assignments and what not). I’m still going though, and with a bit more of a sense of urgency as I have now seen 3 other boards trying to accomplish the same thing. Nothing like a healthy spirit of competition :stuck_out_tongue: Honestly though, this is just for me, but I’m very happy to share what I have with anyone. My battle plan is still cleaning up the layout mistakes, with should be easier with the changes to the power supplies I made.

Have a good one,