Can not display on SHARP AQUOS TV through HDMI

I'm trying to connect Beagleboard to SHARP AQUOS TV through HDMI and
want to display 720p on it, but it does not work well , although I
already successed to connect to PC monitor.

I am using linux-omap-dss kernel and modified default display driver
as
following.

<drivers/video/omap2/displays/panel-generic.c>
static struct omap_panel generic_panel = {
.owner = THIS_MODULE,
.name = "panel-generic",
.init = generic_panel_init,
.enable = generic_panel_enable,
.disable = generic_panel_disable,
.suspend = generic_panel_suspend,
.resume = generic_panel_resume,

.timings = {
#if 0
/* 640 x 480 @ 60 Hz Reduced blanking VESA CVT 0.31M3-R */
.x_res = 640,
.y_res = 480,
.pixel_clock = 23500,
.hfp = 48,
.hsw = 32,
.hbp = 80,
.vfp = 3,
.vsw = 4,
.vbp = 7,
#endif
/*** add form here ***/
.x_res = 1280,
.y_res = 720,
.pixel_clock = 64000,
.hfp = 48,
.hsw = 32,
.hbp = 80,
.vfp = 3,
.vsw = 5,
.vbp = 13,
},

Could anyone let me know proper setting value for AQUOS ??

SHARP AQUOS supports following resolution and frequency.
(not support VESA)

resolution 720p 1280x720
horizontal scan frequency(kHz) 45.0
vertical scan frequency(Hz) 60

TV's often do not support reduced blanking.
You want the latest 2.6.29 kernel, and even then a patch might be
needed for the sync. This is just a two-liner or so but after applying
that it worked on my tv but not any more on my monitor, so guess the
solution is to examine EDID info and act accordingly.
Video mode is called hd720 or 720hd (I forgot).

FM

Thank you FM !!

Here are EDID info got from Windows after converted from DVI to DSUB.

Monitor
  Model name............... REX-VGADVI
  Manufacturer............. Sharp
  Plug and Play ID......... SHP0FDB
  Serial number............ n/a
  Manufacture date......... 2007, ISO week 255

This line

   Modeline............... "1280x720" 74.250 1280 1390 1430 1650 720
725 730 750 +hsync +vsync

suggests that you need +hsync and +vsync.
There is a patch posted/mentioned for thiis, but I do not know exactly
where to vind it.
It involved exchanging the hor fsp with the hor bsp and the ver fsp
with the ver bsp (if I recall the names correctly).
Search the maling list. A few people have been active on this.

Ultimate solution would be to modify the video driver to read the edid
data and act accordingly.
This is not done yet though.

FM.

Bumped upon the pastebin with the patch: http://pastebin.com/m5ea6fd9
note that with this patch it works on my tv, but not on my monitor any
more.

FM

Hi,

Just a thought here, but in my experience, some TVs will not sync onto
1280x720.
Those TVs will sync onto 1360x768 however. We tested this across many
brands to
see what the most common format would be. And most TVs would use the
1360x768 and
quite a few would not come up with the 1280x720. They normally would
just go blank
or say unsupported mode.

I don't work in Linux so I can't offer support there. I just modified
my video driver directly.

I'll try to remember to look up the cpu register settings and post
them later.

GL,
Matt

Here are the settings used for 1360x768

    // 1360x768 60 Hz, 86.4 MHz pixel clock
    // Note: This setting depends on changing BSP_DSS_CLKSEL_DSS1 in
bsp_cfg.h to give a 144MHz DSS1 clock.
    // Note: This setting depends on a nominal value for the DISPC
VCC.

    #define DEFAULT_PIXELTYPE DISPC_PIXELFORMAT_RGB16
    // Note: Setting DEFAULT_PIXELTYPE to DISPC_PIXELFORMAT_RGB32
results in a
    // dramatic drop in performance in the GDI BLTs, cause is not
known.
    //#define DEFAULT_PIXELTYPE DISPC_PIXELFORMAT_RGB32
    //#define DEFAULT_PIXELTYPE DISPC_PIXELFORMAT_ARGB32

    #define LCD_WIDTH 1360
    #define LCD_HEIGHT 768

    // 1676 clocks per line 1360+hsw+hfp+hbp = 1811
    // Note: HWS, HFP and HBP, program desired value - 1
    #define LCD_HSW 63
    #define LCD_HFP 152
    #define LCD_HBP 236

    // 795 lines per frame (795-768=27))
    // Note: for VSW, program desired value - 1
    #define LCD_VSW 4
    // Note: for VFP and VBP, program desired value
    #define LCD_VFP 2
    #define LCD_VBP 20 //20 + 2 + (4+1)=27

    // DSS1 = DPLL4(864)/5 = 172.8Mhz, divide by 2 = 86.4MHz pixel
clock
    // Note: DSS1 clock divider and pixel clock divider are set in src
\inc\bsp_cfg.h
    #define LCD_LOGCLKDIV 1
    // Minimum value for LCD_PIXCLKDIV is 2
    #define LCD_PIXCLKDIV BSP_LCD_PIXCLKDIV

    #define LCD_LOADMODE 0

    // positive H and V sync
    #define LCD_POLFREQ (/* DISPC_POL_FREQ_IVS |
DISPC_POL_FREQ_IHS | */ DISPC_POL_FREQ_ONOFF)

    #define LCD_DEFAULT_COLOR 0x00000000
    #define LCD_TRANS_COLOR 0x00000000

    #define TV_DEFAULT_COLOR 0x00000000
    #define TV_TRANS_COLOR 0x00000000

GL
M