CortexA15 L2 cache enable

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1

Hello all

Do you know , how to enable L2 cache in Beagle-x15 board ?

Searching from google , and linux kernel source .

I dont find any function about the scu config for enable in kernel .

For Cortex-A9 , there will be almost PL310 cache controler , but on Cortex A15 ,intergrated SCU replace the PL310 .

But I dont find any code related .

Does anyone know about this ?

Any idea is welcome and appreciate

Thanks and regards

2

Screw enabling L2 cache, how to get hold of a Beagle-x15 board? :wink:

P.

3

Actually I only have dra752 on hand . not beagleboard x15 .just custom J6 board

4

X15 is coming. Final version is getting ready to be built. Assuming that certain people go on an extended vacation and stop changing things.

Gerald

5

Great news! It’s good you are all taking the time you need to do it right.

6

Hehehe.

Btw missed your reply to me liyaoshi. Much thanks for doing so, apologies for not catching it earlier.

P.

7

So , can we talk about the L2 cache enable now ?