Creating a memory controller inside the FPGA to connect to the BeagleBone stacking connectors

Hi All,
Does anyone have any suggestion for the best way for pinning out a FPGA to BeagleBone (specially the memory bus to BeagleBone)? I am planning to use xilinx XC6SLX45-CSG324. Does anyone know which pins are more suitable for high speed bus, when trying to create memory controller inside the FPGA to connect to the BeagleBone stacking connectors?

I would use the GPMC (General Purpose Memory Controller) bus.


Hi, Pajoom:

If your project is in stage of technical research, I suggest you connect the CPU and FPGA via multi channel, recommand to use I2C/SPI/GPMC/UART.

best regard.

Thanks for your help Gerald. Do you happen to have any document that explains more on this issue?

Thanks for your help Robin. Do you happen to have any document that explains more on this issue?

2012/4/17 Robin Steven <>

No document per se. Other than the TRM for the processor that gives information on access to the Address, Data, CS, RD, and WR lines for a standard memory bus. The multiplexed mode will take up the fewest pins


Hello Nazanin,

I’m coming into this a bit late, but I have been thinking about doing just this with my beaglebone, and that same spartan fpga. Your probably a bit ahead of me right now, for the past week or so, I’ve just been googling for inspiration, and information about how to do the interfacing. As Gerald, and Vortune have mentioned, the gpmc will probably be the best connection for high speed. The SPI, and I2C being also extremely useful. In fact, I came across this, and this guy is using those interfaces. I’ve been using that as the jumping point for ideas, and for things to look for. He is using the Spartan-3 XC3S200AVQ100, but I already have one of those (love it btw), and this is more for the technical challenge, and experience anyway!

For GPMC data, as mentioned, the datasheet ( and TRM ( are great, if hefty tombs :stuck_out_tongue: The TI wiki has some information (,_AM35x,_and_AM-DM37x_GPMC_registers). (Anyone else reading this, how well does this align with the AM335x? is there a better resource specific to it you can recommend?)

This is specific to OMAP ( but the links at the bottom, especially to Philip Balister’s git hub,look promising. If what he has done with gnu radio and omap3/fpga is there, it could be a huge help. I’m not nearly there yet to use that, but it’s nice to know about. Also, I found these two git repositories:;a=blob;f=arch/arm/mach-omap2/gpmc-smc91x.c;h=ba10c24f3d8dcef3378490a9f615c74b471e22a2;hb=56299378726d5f2ba8d3c8cbbd13cb280ba45e4f and;a=blob;f=arch/arm/mach-omap2/gpmc-nand.c;h=c1791d08ae56a5a45847bfd8064213cfe36a6345;hb=56299378726d5f2ba8d3c8cbbd13cb280ba45e4f. Unfortunately, I can’t find the website that linked to them anymore.

And, finally, and assortment of documents I have found on the subject, including code snippets here and there, in decreasing order of usefulness (My opinion after having read them): a freescale chip, but the concepts are still relevant i think),, communication to fpga),,,

Wow, that is quite the brain dump. After reading that, you know what I know. Sorry to anyone else who read that and it was a lot!

I have a couple questions of my own, if anyone can help direct me. I remember seeing someone mentioning that the gpmc lines to the connectors on the beaglebone are not matched lengths. Being a newbie, can someone tell me how much of an impact that would have (the first link mentions it, but doesn’t go into detail)? Could I compensate the lengths on a this fpga cape board to match the lengths? (This is till pretty early, and I’m just asking whats popping into my head).

Nazanin, I’d love to compare notes some time as our two project progress, if your interested. Same goes for anyone else reading this, and is interested.

Have a good one,


I believe that Ettus, who makes hardware for GNUradio (DDS and such), has an embedded version E100/E110, which uses both an FPGA and an OMAP processor, interfaced via the GPMC bus. If I recall there are both PDF schematics on thier site as well as a paper discussing the entire process, methods and such that they used to move data to/from the FPGA/Omap for processing signals and such. I have the paper(s) someplace, need to dig though some folders. However I suspect some time with google would uncover them fairly quickly.

They use GMPC as a bus to talk to/from a specialized ‘co-processor’ for want of a better way to phrase it. For this sort of thing, I think GPMC is ideal. Not sure what your hoping to accomplish with a ‘memory controller’ on an FPGA for the omap however.

Seem to recall a digital camera project that does a similar thing, if I run across that again I’ll try and remember to drop the link in here for your perusal.

Jonathan Smith

Some related documentation:

Talks about both hardware and software side of things. Should at least be a reasonable place to start.