DDR initialisation on PocketBeagle


I’m currently trying to modify the (custom) MLO of my bare metal application in order to work with the PocketBeagle. At the moment this MLO works fine with BBB.

According to the (incredibly small) manual of the Octavo SoC I changed the initialisation of the DDR and EMIF registers - but this does not seem to be everything which is necessary.

Now with these register settings my MLO successfully loads the main application into the DDR RAM but when the SoC jumps to the start adress of it, it stalls. So it seems there is still a problem with the RAM initialisation. Either writing the application to the RAM does not work or execution of the loaded application is not possible.

What I can see at the moment: the BBB initialisation of the RAM contains a lot more than shown in the Octavo manual, there are a lot of idle and shut-down states set which are not mentioned in Octavo manual.

So…any idea what else is different in initialisation of BBB and PocketBeagle? Are these additional idle/shut-down register settings needed too?


You could write a memory compare check in MLO to see that the file is indeed loaded correctly to help debug the problem. I wrote a routine to write the memory address to each cell in memory and then compare. Not totally comprehensive for stuck bits, but gave a warm fuzzy that memory was somewhat ok. Writing all 1’s and then all 0’s and compare would be another memory test.

Finally I could solve the problem: the guys from https://sourceforge.net/projects/starterwarefree/ have implemented support for PocketBeagle in their MLO. Not sure what the difference is to my code but theirs is working smoothly, now my application starts as expected.