Delay between SPI CS and clock

Hi there

I want to send some data to a micro controller with a beaglebone black (beagle bone is master). As shown in the picture, the delay between falling edge of cs and first rising edge of clock is too much. could you please tell me how to decrease it? the image is taken from a logic analyzer which its sampling rate is lower than SPI bitrate.

thanks a lot.

cs.PNG

On Mon, 17 Jun 2019 05:44:09 -0700 (PDT),
hamidkavianathar@gmail.com declaimed the
following:

I want to send some data to a micro controller with a beaglebone black
(beagle bone is master). As shown in the picture, the delay between falling
edge of cs and first rising edge of clock is too much. could you please
tell me how to decrease it? the image is taken from a logic analyzer which
its sampling rate is lower than SPI bitrate.

  Why does it matter? Chip Select serves to "wake up" the target chip,
making it ready to respond to the clock changes. Some targets may need the
time to activate circuits. Data transfer is done on the clock transitions.
A circuit with a single target could, in theory, have the CS line tied
permanently using a pull-up/pull-down resistor (since you state a falling
edge, I'd guess pull-down to ground would be the permanent mode).

Dennis:
Be careful. Many/most SPI slave devices use the rising edge of the CS line, following the write activity, to load the data and make it active.
So, you load it serially, but it is not transferred into the active control or output registers, until CS goes high, making it all take effect simultaneously.
CS is typically required, even with a single SPI slave on a bus, depending on how the specific SPI slave works.
— Graham

thanks for comment. there is a microcontroller on the other side. the spi works fine. I send data to microcontroller and can read from it properly. but I want to have faster communication. in fact I don’t need CS at all.

thanks for comment. there is a microcontroller on the other side and I want to have faster communication.