As written in previous mail, it seems that we can't get pixel clock > 72MHz with DPLL4 without e.g. breaking 96MHz clock. Somebody mentioned that it could be possible to configure DSI PLL to create max 173MHz clock to create max 86.5MHz pixel clock.
Anybody with DSI PLL sample code, ideally programming it to 173MHz? Or any other hints?
As written in previous mail, it seems that we can't get pixel clock >
72MHz with DPLL4 without e.g. breaking 96MHz clock. Somebody mentioned
that it could be possible to configure DSI PLL to create max 173MHz
clock to create max 86.5MHz pixel clock.
Anybody with DSI PLL sample code, ideally programming it to 173MHz? Or
any other hints?
I'm interested in this as well. Sadly, I haven't figured out how to
make it work.
As written in previous mail, it seems that we can't get pixel clock > 72MHz with DPLL4 without e.g. breaking 96MHz clock. Somebody mentioned that it could be possible to configure DSI PLL to create max 173MHz clock to create max 86.5MHz pixel clock.
Anybody with DSI PLL sample code, ideally programming it to 173MHz? Or any other hints?
I'm interested in this as well. Sadly, I haven't figured out how to
make it work.