DSS fixes

Hi,

I made some fixes to my new display subsystem code. The clock calculations were a bit faulty. With the new version you should get 61Hz refresh rate with 1024x768 DVI resolution. Also using DSI DPLL should not crash the kernel.

Some other changes included:

  • No double allocating of DVI power GPIO
  • 640x480 resolution for DVI
  • OmapFB panning support
  • suspend/resume for DVI

However, the sync lost problem is still there.

The changes are in the master branch at http://www.bat.org/~tomba/git/linux-omap-dss.git/

The tree has been rebased, so you’ll first have to throw away the old version.

Tomi

Hi,
     is this sync lost problem you are talking abt is
DISPC_IRQ_SYNC_LOST? [exact error: omapfb omapfb: irq error status
4000] I am getting this if I issue bootcmds faster. <not satisfied as
I can reproduce only certain times> But I saw that SDIO HC starts
working if sync lost issue happens. Any idea why? I just posted
detailed logs under name: "strange behavior: "omapfb omapfb: irq
error status 4000" and SDIO support for beagle".

Thanks
p

I made some fixes to my new display subsystem code. The clock calculations

I just tried 1024x768@60 (I used your config from your previous mail).
The first boot my monitor shuts off and I got the boot messages:

Power Management for TI OMAP3.
Unable to set state of powerdomain: sgx_pwrdm
Failed to setup powerdomains
omap2|3_pm_init failed: -22
VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 1
omap-dss DISPC error: Requested pixel clock not possible with the
current OMAP2_DSS_MIN_FCK_PER_PCK
setting. Turning the constraint off.
omap-dss DISPC error: Requested pixel clock not possible with the
current OMAP2_DSS_MIN_FCK_PER_PCK
setting. Turning the constraint off.
omap-dss DISPC error: Requested pixel clock not possible with the
current OMAP2_DSS_MIN_FCK_PER_PCK
setting. Turning the constraint off.
Console: switching to colour frame buffer device 128x48
omap-dss DISPC error: Requested pixel clock not possible with the
current OMAP2_DSS_MIN_FCK_PER_PCK
setting. Turning the constraint off.
clock: clksel_round_rate_div: dpll4_m4_ck target_rate 86400000
clock: new_div = 5, new_rate = 86400000
omap-dss: Could not find exact pixel clock. Requested 56000 KHz, got 57600 KHz.
omap-dss DISPC error: dispc irq error status 4024
omap-dss DISPC error: dispc irq error status 4000
omap-dss DISPC error: dispc irq error status 4000
omap-dss DISPC error: dispc irq error status 4000
omap-dss DISPC error: dispc irq error status 4022
omap-dss DISPC error: dispc irq error status 4000
omap-dss DISPC error: dispc irq error status 4000
omap-dss DISPC error: dispc irq error status 4000
omap-dss DISPC error: dispc irq error status 4022
omap-dss DISPC error: dispc irq error status 4000
omap-dss DISPC error: Excessive DISPC errors
Turning off lcd and digit
omap-dss DISPC error: Excessive DISPC errors
Turning off lcd and digit
omap-dss DISPC error: Excessive DISPC errors
Turning off lcd and digit
omap-dss DISPC error: Excessive DISPC errors
Turning off lcd and digit
twl4030_rtc twl4030_rtc: setting system clock to 2000-01-01 00:00:00
UTC (946684800)

The second boot I got 1024x768@62Hz (this is what my monitor says) and
these bootmessages:

Power Management for TI OMAP3.
Unable to set state of powerdomain: sgx_pwrdm
Failed to setup powerdomains
omap2|3_pm_init failed: -22
VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 1
omap-dss DISPC error: Requested pixel clock not possible with the
current OMAP2_DSS_MIN_FCK_PER_PCK
setting. Turning the constraint off.
omap-dss DISPC error: Requested pixel clock not possible with the
current OMAP2_DSS_MIN_FCK_PER_PCK
setting. Turning the constraint off.
omap-dss DISPC error: Requested pixel clock not possible with the
current OMAP2_DSS_MIN_FCK_PER_PCK
setting. Turning the constraint off.
Console: switching to colour frame buffer device 128x48
omap-dss DISPC error: Requested pixel clock not possible with the
current OMAP2_DSS_MIN_FCK_PER_PCK
setting. Turning the constraint off.
clock: clksel_round_rate_div: dpll4_m4_ck target_rate 86400000
clock: new_div = 5, new_rate = 86400000
omap-dss: Could not find exact pixel clock. Requested 56000 KHz, got 57600 KHz.
twl4030_rtc twl4030_rtc: setting system clock to 2000-01-01 00:00:00
UTC (946684800)

I will run more tests.

Robert

I will run more tests.

I tried 640x480@60Hz and got exaclty 640x480@60Hz. :slight_smile:
Also I got no error messages while booting:

...
OMAP DMA hardware revision 4.0
USB: No board-specific platform config found
OMAP DSS rev 2.0
OMAP DISPC rev 3.0
OMAP VENC rev 2
i2c_omap i2c_omap.1: bus 1 rev3.12 at 2600 kHz
twl4030: PIH (irq 7) chaining IRQs 368..375
twl4030: power (irq 373) chaining IRQs 376..383
twl4030: gpio (irq 368) chaining IRQs 384..401
...

Had you found the time to implement FBIOGET_VBLANK?

Robert.

I forgot one thing: it would be good if it is possible to configure
the pixel clock via a boot parameter so one is able to fine-tune the
dvi frequence.

Robert

You need to turn the OMAP2_DSS_MIN_FCK_PER_PCK Kconfig option to 0 when
using modes with high pixel clock (basically anything with DVI). I think I
did that change for the beagle defconfig...

  Tomi

uImage with the update DSS2:

http://dominion.thruhere.net/koen/OE/uImage-2.6.27+2.6.28-rc3+r2+gitr444fcab6e8f8bad4ffc50feb91516c246d91e901-r2-beagleboard.bin

regards,

Koen

Hiya,

I just updated the master branch with a small fix that fixes the sync
lost problem for me.

Now I can load/unload the DSS modules in a loop for a long time.
Previously I always got sync losts in ~10 tries or so.

Tomi