EMAC RMII Setup

Hi

I’ve notice a couple of threads that talk about people using the RMII interface
and there being some issues. However, I haven’t seen any resolutions posted.

I have gotten the interface to do the negotiation for link and speed.
This all seems to happen over the MDIO interface.

When it gets to DHCP - it times out.
I don’t see any traffic over the RX or TX lanes of the RMII interface
and I don’t see any packet requests via Wireshark.

However, there is a lot of traffic over the MDIO interface while waiting for time out.

I can only infer on this that I am missing something in the software side
of the setup.

I am working in CE7, but would welcome any feedback from the Linux or
other OS folks as it will likely be applicable just not identical.

I’ve gone through this as far as a hardware guy knows how. I could use
some pointers from the software people out there.

Things that I know needed to be done:
Set GMII_SEL_REG to 0xF5
this sets the reference clocks to inputs from the phys
also sets the ports to RMII mode vs MII or RGMII.

Set pad configs to:

PAD_ENTRY(MII1_RXERR, MODE(1) | RXACTIVE) /* RMII1_RXERR (J15)i - RMII1_RXERR /
PAD_ENTRY(MII1_TXEN, MODE(1)) /
RMII1_TXEN (J16)o - RMII1_TX_EN /
PAD_ENTRY(MII1_CRS, MODE(1) | RXACTIVE) /
RMII1_CRS_DV (H17)i - RMII1_CRS_DV /
PAD_ENTRY(MII1_TXD1, MODE(1)) /
RMII1_TXD1 (K16)o - RMII1_TXD1 /
PAD_ENTRY(MII1_TXD0, MODE(1)) /
RMII1_TXD0 (K17)o - RMII1_TXD0 /
PAD_ENTRY(RMII1_REFCLK, MODE(0) | RXACTIVE) /
RMII1_RXCLK (H18)i - RMII1_REFCLK /
PAD_ENTRY(MII1_RXD1, MODE(1) | RXACTIVE) /
RMII1_RXD1 (L15)i - RMII1_RXD1 /
PAD_ENTRY(MII1_RXD0, MODE(1) | RXACTIVE) /
RMII1_RXD0 (M16)i - RMII1_RXD0 /
PAD_ENTRY(GPMC_WPN, MODE(3) | RXACTIVE) /
RMII2_RXERR (U17)i - RMII2_RXERR /
PAD_ENTRY(GPMC_A0, MODE(3)) /
RMII2_TXEN (R13)o - RMII2_TXEN /
PAD_ENTRY(GPMC_WAIT0, MODE(3) | RXACTIVE) /
RMII2_CRS_DV (T17)i - RMII2_CRS_DV /
PAD_ENTRY(GPMC_A4, MODE(3)) /
RMII2_TXD1 (R14)o - RMII2_TXD1 /
PAD_ENTRY(GPMC_A5, MODE(3)) /
RMII2_TXD0 (V15)o - RMII2_TXD0 /
PAD_ENTRY(MII1_COL, MODE(1) | RXACTIVE) /
RMII2_RXCLK (H16)i - RMII2_REFCLK /
PAD_ENTRY(GPMC_A10, MODE(3) | RXACTIVE) /
RMII2_RXD1 (T16)i - RMII2_RXD1 /
PAD_ENTRY(GPMC_A11, MODE(3) | RXACTIVE) /
RMII2_RXD0 (V17)i - RMII2_RXD0 /
PAD_ENTRY(MDIO_DATA, MODE(0) | RXACTIVE | PULLUP_EN) /
MDIO_DATA /
PAD_ENTRY(MDIO_CLK, MODE(0) | PULLUP_EN) /
MDIO_CLK */ \

If anyone see something I did wrong or knows of additional things I need to do, I’d appreciate the insight.

Thanks,
Matt

Hi All,

In addition to the above, found that I needed to set a bit or two (1 port or 2) in the MACCONTROL reg.
The routine I found changed to this (CE7 file cpsw3g.c)

BOOL Cpsw3g_get_phy_link_state(UINT32 port)
{
UINT16 phy_id;
int speed = 0, duplex = 0;
UINT16 reg;
UINT32 mac_control = 0;

BOOL link = FALSE;

PCpswCb pCpsw3gCb=&g_cpsw3gCb;

phy_id = pCpsw3gCb->phy_id;

if (MdioRd(phy_id, PHY_BMSR, 0, &reg))
return link; /* could not read, assume no link */

if (reg & PHY_BMSR_LS) { /* link up */
speed = Phy_speed(phy_id);
duplex = Phy_duplex(phy_id);

link = TRUE;
mac_control = (1 << 5); /* MIIEN /
if (speed == 10)
mac_control |= (1 << 18); /
In Band mode */

// ***** added these lines *****
if (speed == 100)
mac_control |= (1 << 15); /* RMII Gasket 100Mb Mode */
// ***** add bit 16 for 2nd port if needed

if (speed == 1000)
mac_control |= ((1 << 7) | (1 << 17)); /* GIGABITEN | GIGABIT_FORCE /
if (duplex == FULL)
mac_control |= (1 << 0); /
FULLDUPLEXEN */
}

if (mac_control == pCpsw3gCb->mac_control)
return link;

if (mac_control)
{
OALMSGS(OAL_ERROR, (
L"link up on port %d, speed %d, %s duplex\r\n", port, speed,
((duplex == FULL) ? L"full" : L"half") ));
OALMSGS(OAL_ERROR, ( L"Mac Ctrl: %x\r\n", mac_control));
}
else
{
OALMSGS(OAL_ERROR, ( L"link down on port %d\r\n", port));
}

Cpsw3g_Write_Register((UINT32 *)CPMAC_MAC_CTRL(port), mac_control);
pCpsw3gCb->mac_control = mac_control;

return link;
}

Hope this helps someone.
Still testing to see if that’s all that’s needed.
At least it’s getting the DHCP and doing the BOOTME now.

Again, if anyone knows of anything else that I may have missed. I’d appreciate the feedback.

Thanks,
Matt