ETM registers access

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1

Hello,
when looking at the various documents available, I didn't find any
mention of ETM registers being memory-mapped
(at least, it doesn't show in the list of peripherals in the TRM).

Can anyone confirm that ETM registers are not accessible by embedded
software (only JTAG access is implemented) in OMAP3530?
This is typically an option selected at SoC integration time (by
designers).

Thanks in advance,
Alain

2

Hello Alain

Hello,
when looking at the various documents available, I didn't find any
mention of ETM registers being memory-mapped
(at least, it doesn't show in the list of peripherals in the TRM).

The preliminary documentation that was sent to me because of my jtag work
has the following to say about this

Debugger Address Space
The CoreSight components are interfaced with the TAP router through the DAP. As
recommended by the CoreSight architecture the DAP is directly interfaced to the
OMAP3430 bus. The debugger can directly access the entire memory space without
requiring the processor entering the debug state and being programmed
with a load or
store instruction.
The following modules are mapped to the DAP address space.

Start Addr(Hex) | End Addr (Hex) | Size | Description
0xD401 0000 | 0xD401 0FFF | 4K | ETM module
0xD401 1000 | 0xD401 1FFF | 4K | CortexA8 module
0xD401 9000 | 0xD401 9FFF | 4K | TPIU
0xD401 B000 | 0xD401 BFFF | 4K | ETB module

The DBGEM signal on the CortexA8 is driven by setting bit 13 at
address 0xD401D030
in the DAP-APB address space.

OpenOCD now has JRC control so somebody could state playing with all this

3

Kees,

sounds good! Thanks for the quick answer!
What is the document you're referring to? Do you have the name and/or
location?
I have a TI CD for OMAP35x that I got from the ARM developper's
conference earlier this year in Santa Clara. Maybe I already have it.

Thanks again,

Kind regards,
Alain