Hi there,
I am currently working on a project that involves setting up SPI with flow control between my BeagleBone and an Atmel uC (32 bits) to transfer large bytes of data preferably greater than 200 in one write cycle. My idea for flow control is as follows-
1)Enable both master and slave with slave in idle state
2) Master sends a command such as 0xAAFFFFFF and the DMA interrupt handler in the slave gets called on having received data. Depending on the state the slave is in, this data gets interpreted as a command or data. My slave interprets this as command and replies with 0xAAAAFFFF that signals the master to send actual data.
3)As a result, the DMA interrupt handler on the master side gets called when data is received from the slave on the master DMA receive channel. The master then performs the data transfer and so on.
I have successfully implemented this on two 32 bit Atmel uC’s and now want to implement this on BeagleBone.
From having goggled extensively I understand that the DMA gets automatically invoked by the SPI driver when the data transfer limit exceeds a threshold of 160 bytes mentioned in omap2_mcspi.c. I want to enable a DMA/SPI Handler(whichever is possible) in a kernel module that gets called when I receive some information by slave. I know how to enable gpio interrupts/handlers but cant find any information for SPI.
How do I do this?
I am looking at data transfer speeds of > 4Mbps
Would implementing my idea in userspace using spidev and using a blocking transfer operation help me achieve the above task.
Which method is better and provides least latency?