GPIO / expansion connector

I have a C2 Beagle Board, and am trying to work up an 8-bit
bidirectional interface.
I am very confused by the Beagle Board document related to the pin
I selected GPIOs 136 - 143 as a byte-aligned group of 8 contiguous
bits. But, GPIO_140, 141 and 142 seem to not be brought out to pins
4, 10 and 6 respectively. I assume this has something to do with the
gray bars on Table 20. Is there a setting of the interconnect mapping
that will switch those GPIOs to the appropriate OMAP pads? I haven't
found out how to do that yet.

The reason I'm concerned about byte alignment is I can just do a byte
write to the right byte and not have to read, mask and then or in the
byte to be written. Due to the slow GPIOs (250 ns for each read and/
or write access) I'd much rather do the byte access.

(In other topics, I'm still waiting to hear from TI about the slow
GPIO, it has been 2 weeks with no response! Yes, I called them, they
couldn't track down the person working on it. GREAT customer support


The gray areas in the table are the pins that are NOW connected to the expansion connector on a rev C board. The ones above are the ones that are connected on a Rev B board. Each pin on the OMAP3530 can have multiple functions on that pin. The GPIO pins are group in increments of 32. What this means is that GPIO132 thru GPIO 139 are all contiguous and reside in GPIO Group2.

In order to configure those pins to show up on the expansion connector, you must set the pin mux register, set the mode as input or output, and set whatever pullup configuration you need. You will need to use the GPIO_DATAOUT register to control these pins or the GPIO_DATAIN register to read them…

Chapter 24 of the OMAP3530 Technical Reference Manual describes the setting up of the GPIO pins. I suggest you look that over to get an idea of how all that works and the appropriate register settings required and how to communicate to them…


Arrgh! So the Rev B HAD a byte-aligned group of 8 bits, the Rev C
Groan! That, right there, may halve the rate you can access the the
port I am
trying to make. Maybe I can get away with a 16-bit access without
stepping on any other
bits that are used by something else. (I've already crashed it about
15 times finding
out what I can and can't touch.)



Ahhh, a successful result! I can get away with accessing the
contiguous low 16 bits of GPIO 5 without breaking anything. So, I can
then control my byte of non-aligned I/O without having to read/modify/
write. That lets me update every 250 ns or so, which will be fast
enough for many of the things I'm working on.

Thanks for the clarification of the gray bars on Table 20, I think it
USED to say what those meant, but the latest manual seems to have
dropped that line. Since the new manual is for Rev. C boards only,
the gray bars and the pin assignments within them should just be


I have an updated version coming out in a week or so. I will make the change there. Glad you had a little success!