I have a BBB project which makes extensive use of the AM3359’s GPMC peripheral.
I’m trying to assess what it would take to port it to the BeagleV Fire. Is there an equivalent way to control external memory through the P8/P9 headers? Precise pin compatibility is not a requirement.
Tangentially, is there a technical reference manual available for the MPFS025T? The docs I can find online are only a few hundred pages long, and only cover properly powering the package. Not anywhere close to the level of depth that the AM3359’s 5000 page TRM with programming models and notes on each peripheral register.
You are describing UIO. To use this you need to craft an entry in the device tree, but you don’t need to write any drivers. You use device-tree to tell Linux where your bus lives in physical address space and tie it to the uio device driver. Then your user code can mmap() the /dev/uioX device and (assuming your FPGA logic is properly bridging between the internal buses and your external bus) the bus transactions will show up on the I/O pins.
The HSIOs are not fast enough for PCIe. You need to use the tranceivers signal pairs for PCIe. There are two pairs you can use on the SYZYGY connector for PCIe.
it’s just too powerful…