GPMC issue -- inductive cross-talk?

I am working on a design where the BBB configures an FPGA using the GPMC interface.
We find that this configuration fails perhaps one out of ten times.
When we probe the signals, we see a large glitch developed on the clock line, and suspect that this is occasionally being caught as an extra edge by the FPGA and corrupting the configuration data.

It seems that there are two likely contributors to this problem:

  1. Our board design has long traces from the BBB to the FPGA and we are violating the capacitive load limits for the uP’s IO pins.
    While the IO pins are specified to produce 6 mA output current, the rise and fall times we measure are consistent with something more like 20 mA being sourced/sunk during each transition of the data pins.

  2. The BBB’s P8 header has only 2 ground pins to support a 16-bit parallel data bus.
    This leads to a possibility for inductive coupling between the data lines and the clock line (for example).
    Of course this is made worse by our design having excess load capacitance resulting in larger current transients.

Has anyone experienced similar issues?
Does my analysis of the likely root cause make sense?
Does anyone know of a reference design showing buffering on the GPMC signals to avoid this kind of issue?



How fast are you running the GPMC?

Why are you using the clock?