I’m trying to generate 8 channel I2S audio with BBB.
I’d like to use these data output pins:
P9_28 - C12/2 - mcasp0_axr2
P9_27 - C13/2 - mcasp0_axr3
P9_30 - D12/0 - mcasp0_axr0
P9_41 - D13/0 - mcasp0_axr1
I’ve set pinctrl-single:
- 0x1a8 0x08 /* mcasp0_axr1, MUX_MODE0 | PIN_OUTPUT */
- 0x1b4 0x2f /* xdma_event_intr1.gpio0_20, MUX_MODE7 | PIN_INPUT */
And also I’ve removed all other occurences of 0x1b4 and 0x1a8 from the device tree.
The problem is that on P9_41 there is not AXR1 output, but 0.3V signal with some EMI spikes of 32.768kHz frequency generated probably by CLKOUT2.
If I route AXR1 to P8_31 instead of P9_41 the multichannel audio works fine. But I’d like to have HDMI output, which required P8_31.
The BBB_SCH.pdf is a bit different regarding those pins than it is draw on gerber files.
There is chance that desoldering R19 could help, if the 0.3V and EMI spikes are generated by CLKOUT2 processor pin. But I’ve not tried that. Moreover CLKOUT2 pin is routed also to JTAG P2 header, so there is chance that unwanted 32.768kHz signal is received on that trace.
Just after the posting I’ve found the source of reported error.
The Angstrom DTS file contains following pinctrl request in the DTS for HDMI audio.
0x1a8 0x1f /* mcasp0_axr1 GPIO1_27 | OUTPUT | PULLUP /
mcasp_clock_enable = <&gpio2 27 0>; / BeagleBone Black Clk enable on GPIO1_27 */
It is false, because clock control is on gpio3.
Correct configuration register should be different:
0x06c 0x17 /* gpmc_a11.gpio3_21, MUX_MODE7 | PIN_OUTPUT */
I’ve been using this without checking.
After fixing this, the AXR1 output is correctly generated (and not overriden by later request in the same pinctrl-single line.
You might want to double check what you are doing here. The clock control is on gpio1_27 as shown on page 3 of the schematic. Pin V17 is hardwired to the output enable of the 24.576 MHz oscillator. It can turn the oscillator on or off. This output must be turned on to use the HDMI audio.
Gpio3_21 is connected to the oscillator output and used as a high speed clock input when the SOC is driving audio to the HDMI framer. If the oscillator output is disabled by gpio1_27 then the gpio3_21 pin can be used for other functions.
you are right.
I’ve been mixing configuration register offsets and their names. But I’ve managed finally to get it right.
It would help if the conf_* registers were predefined in the header and cape DTS files would use that defines.