how to make pwm_P8_13 low on boot?

Hi,

I’m trying to use pwm on BBB
Linux beaglebone 3.8.13-bone50 #1 SMP Tue May 13 13:24:52 UTC 2014 armv7l GNU/Linux
I have modified uEnv.tx

cape_enable=capemgr.enable_partno=BB-UART1,SPI-4SS,bone_eqep2b,bone_pwm_P8_13,am33xx_pwm

and /etc/default/capemgr

Options to pass to capemgr

CAPE=SPI-4SS,bone_eqep2b,bone_pwm_P8_13,am33xx_pwm

after booting I have correctly in slots
0: 54:PF—
1: 55:PF—
2: 56:PF—
3: 57:PF—
4: ff:P-O-L Bone-LT-eMMC-2G,00A0,Texas Instrument,BB-BONE-EMMC-2G
5: ff:P-O-L Bone-Black-HDMI,00A0,Texas Instrument,BB-BONELT-HDMI
7: ff:P-O-L Override Board Name,00A0,Override Manuf,BB-UART1
10: ff:P-O-L Override Board Name,00A0,Override Manuf,bone_pwm_P8_13
11: ff:P-O-L Override Board Name,00A0,Override Manuf,am33xx_pwm
12: ff:P-O-L Override Board Name,00A0,Override Manuf,SPI-4SS
13: ff:P-O-L Override Board Name,00A0,Override Manuf,bone_eqep2b

and pwm works, but,

  • after power on the logic level on P8_13 is low (as I want it to be)
  • after that (loading dtc overlay) the logic level on P8_13 become high (I dont want it)

My attempt to modify /lib/firmware/bone_pwm_P8_13-00A0.dts and then recompiling doesn’t effect any of:
/sys/devices/ocp.3/pwm_test_P8_13.11/ duty, period, polarity, run, …

As I don’t want the motor connected to PWM to run, before the applications takes over the control,
can anyone help me to achieve it?

Jan

the values in /sys/devices/ocp.3/pwm_test_P8_13/11 are:
duty 0
period 500000
polarity 1
run 1
after the device tree overlay is loaded.
Does anyone know if possible and if yes how to change them (the default values)?
The changes to corresponding *.dtbo file doesn’t change them.

I don't know if this will help, but have you tried changing the polarity of the PWM pin in the device tree overlay?

      bs_pwm_test_P8_13 {
        compatible = "pwm_test";
        pwms = <&ehrpwm2 1 500000 0>;
        pwm-names = "PWM_P8_13";

        pinctrl-names = "default";
        pinctrl-0 = <&bs_pwm_P8_13_0xc>;
    
        enabled = <1>;
        duty = <0>;
        status = "okay";
          };

The last numeric parameter of pwms <&ehrpwm2 1 500000 0> swaps the polarity of the PWM output.
With the default duty cycle of 0, the pin will be low on power-up.

- after power on the logic level on P8_13 is low (as I want it to be)

- after that (loading dtc overlay) the logic level on P8_13 become high
(I dont want it)

Sorry, I missed this. The 74HC04 would work if it started high and stayed
that way. Do you need to use an overlay? Maybe if you modified the
initial device tree, perhaps with Roberts system for the 3.14 kernel it
would start high and you could flip it.

Thanks Peter,

I have exercised that option already before posting and somehow it didn’t work.

Changing the parameters (and recompiling) didn’t change the default values, so my conclusion is that they might be

somehow hard-coded in a kernel driver.

Jan

Thanks Jason,

There is a hardware solution to my problem in a form of a tiny logic 08 (AND gate). The PWM is connected to one input and an extra ENABLE signal from GPIO is connected to another input. On the output the resulting gated PWM signal will appear when the ENABLE signal goes high from the application.
The solution however is non-elegant and can be avoided if I had a better knowledge of the software - in this case a PWM driver and it’s interaction with a device tree overlay.

The inverter is not a solution as on boot initial pin value is low and after the device tree is loaded it jumps high until the application software (controlling pwm) takes over.
I will use it as a temporary solution.

Cheers

Jan