It should already be on the flashed image, however you will need to add it to extlinux.conf
1 Like
Got it. Iāll give it a try.
When you finish overlaying up to .dtbo, now you need to insert a pin.
SS for P9_17 pin
P9_22 : SCK
P9_21 : MOSI
P9_18 : MISO
P_1 : GND
P_6: 3.3V
P_9: RST
I am trying to connect the RFID RC522 and BBAI-64 board as above. Did I read the data sheet correctly?
Sorry for asking too many questions. I have a lot of questions, but this is the only place to ask them.
Iād route this to a generic gpio, so you can actually control reset from the bbai64ā¦ (in the overlay wire it as an āledā that you can turn on and offā¦)
Regards,
1 Like
Currently, BONE-SPI0_0.dtbo file is written in extlinux.conf.
Now, for pin registration, enter echo {gpio number} > export the gpio pin,
An error such as echo: write error: invalid argument occurs.
So I looked at the gpio pins currently in use with the cat /sys/kernel/debug/gpio command.
The information about the pins mentioned above came out as below.
gpio-328 (P9_17A)
gpio-415 (P9_17B)
gpio-340 (P9_18A)
gpio-420 (P9_18B)
gpio-339 (P9_21A)
gpio-390 (P9_21B)
gpio-338 (P9_22A (BOOTMODE1))
gpio-391 (P9_22B)
Now, to use each pin as spi6_cs0, spi6_d1, spi6_d0, spi6_clk of MODE No. 4
beagleboard/BeagleBoard-DeviceTrees/blob/v5.10.x-ti-unified/pinmux/bbai64.dts The contents of that URL
/* P9_17 (AC21/AA3) PRG1_PRU1_GPO7/SPI0_D1 (gpio0_28/gpio0_115) AC21_AA3 /
BONE_PIN(P9_17, default, P9_17A(PIN_INPUT, 7) P9_17B(PIN_INPUT, 7))
BONE_PIN(P9_17, pruout, P9_17A(PIN_OUTPUT, 0) P9_17B(PIN_INPUT, 7)) / prg1_pru1_gpo7 /
BONE_PIN(P9_17, pruin, P9_17A(PIN_INPUT, 1) P9_17B(PIN_INPUT, 7)) / prg1_pru1_gpi7 /
BONE_PIN(P9_17, gpio, P9_17A(PIN_INPUT, 7) P9_17B(PIN_INPUT, 7)) / gpio0_28 /
BONE_PIN(P9_17, gpio_pu, P9_17A(PIN_INPUT_PULLUP, 7) P9_17B(PIN_INPUT, 7))
BONE_PIN(P9_17, gpio_pd, P9_17A(PIN_INPUT_PULLDOWN, 7) P9_17B(PIN_INPUT, 7))
BONE_PIN(P9_17, i2c, P9_17A(PIN_INPUT, 7) P9_17B(PIN_INPUT_PULLUP, 2)) / i2c6_scl /
BONE_PIN(P9_17, spi, P9_17A(PIN_OUTPUT, 4) P9_17B(PIN_INPUT, 7)) / spi6_cs0 */
/* P9_18 (AH22/Y2) PRG1_PRU1_GPO19/SPI1_D1 (gpio0_40/gpio0_120) AH22_Y2 /
BONE_PIN(P9_18, default, P9_18A(PIN_INPUT, 7) P9_18B(PIN_INPUT, 7))
BONE_PIN(P9_18, pruout, P9_18A(PIN_OUTPUT, 0) P9_18B(PIN_INPUT, 7)) / prg1_pru1_gpo19 /
BONE_PIN(P9_18, pruin, P9_18A(PIN_INPUT, 1) P9_18B(PIN_INPUT, 7)) / prg1_pru1_gpi19 /
BONE_PIN(P9_18, gpio, P9_18A(PIN_INPUT, 7) P9_18B(PIN_INPUT, 7)) / gpio0_40 /
BONE_PIN(P9_18, gpio_pu, P9_18A(PIN_INPUT_PULLUP, 7) P9_18B(PIN_INPUT, 7))
BONE_PIN(P9_18, gpio_pd, P9_18A(PIN_INPUT_PULLDOWN, 7) P9_18B(PIN_INPUT, 7))
BONE_PIN(P9_18, i2c, P9_18A(PIN_INPUT, 7) P9_18B(PIN_INPUT_PULLUP, 2)) / i2c6_sda /
BONE_PIN(P9_18, spi, P9_18A(PIN_OUTPUT, 4) P9_18B(PIN_INPUT, 7)) / spi6_d1 */
/* P9_21 (AJ22/U28) PRG1_PRU1_GPO18/RGMII5_TD0 (gpio0_39/gpio0_90) AJ22_U28 /
BONE_PIN(P9_21, default, P9_21A(PIN_INPUT, 7) P9_21B(PIN_INPUT, 7))
BONE_PIN(P9_21, pruout, P9_21A(PIN_OUTPUT, 0) P9_21B(PIN_INPUT, 7)) / prg1_pru1_gpo18 /
BONE_PIN(P9_21, pruin, P9_21A(PIN_INPUT, 1) P9_21B(PIN_INPUT, 7)) / prg1_pru1_gpi18 /
BONE_PIN(P9_21, gpio, P9_21A(PIN_INPUT, 7) P9_21B(PIN_INPUT, 7)) / gpio0_39 /
BONE_PIN(P9_21, gpio_pu, P9_21A(PIN_INPUT_PULLUP, 7) P9_21B(PIN_INPUT, 7))
BONE_PIN(P9_21, gpio_pd, P9_21A(PIN_INPUT_PULLDOWN, 7) P9_21B(PIN_INPUT, 7))
BONE_PIN(P9_21, pwm, P9_21A(PIN_INPUT, 7) P9_21B(PIN_OUTPUT, 6)) / ehrpwm1_a /
BONE_PIN(P9_21, spi, P9_21A(PIN_OUTPUT, 4) P9_21B(PIN_INPUT, 7)) / spi6_d0 */
/* P9_22 (AC22/U29) PRG1_PRU1_GPO17/RGMII5_TXC (gpio0_38/gpio0_91) AC22_U29 /
BONE_PIN(P9_22, default, P9_22A(PIN_INPUT, 7) P9_22B(PIN_INPUT, 7))
BONE_PIN(P9_22, pruout, P9_22A(PIN_OUTPUT, 0) P9_22B(PIN_INPUT, 7)) / prg1_pru1_gpo17 /
BONE_PIN(P9_22, pruin, P9_22A(PIN_INPUT, 1) P9_22B(PIN_INPUT, 7)) / prg1_pru1_gpi17 /
BONE_PIN(P9_22, gpio, P9_22A(PIN_INPUT, 7) P9_22B(PIN_INPUT, 7)) / gpio0_38 /
BONE_PIN(P9_22, gpio_pu, P9_22A(PIN_INPUT_PULLUP, 7) P9_22B(PIN_INPUT, 7))
BONE_PIN(P9_22, gpio_pd, P9_22A(PIN_INPUT_PULLDOWN, 7) P9_22B(PIN_INPUT, 7))
BONE_PIN(P9_22, i2c, P9_22A(PIN_INPUT, 7) P9_22B(PIN_INPUT_PULLUP, 2)) / i2c6_scl /
BONE_PIN(P9_22, pwm, P9_22A(PIN_INPUT, 7) P9_22B(PIN_OUTPUT, 6)) / ehrpwm1_b /
BONE_PIN(P9_22, spi, P9_22A(PIN_OUTPUT, 4) P9_22B(PIN_INPUT, 7)) / spi6_clk */
Based on the information above, we selected the following.
BONE_PIN(P9_17, spi, P9_17A(PIN_OUTPUT, 4) P9_17B(PIN_INPUT, 7)) // Select P9_17A of SS pin
BONE_PIN(P9_18, spi, P9_18A(PIN_OUTPUT, 4) P9_18B(PIN_INPUT, 7)) // Select P9_18A of MISO pin
BONE_PIN(P9_21, spi, P9_21A(PIN_OUTPUT, 4) P9_21B(PIN_INPUT, 7)) // Select P9_21A of MOSI pin
BONE_PIN(P9_22, spi, P9_22A(PIN_OUTPUT, 4) P9_22B(PIN_INPUT, 7)) // Select P9_22A of SCK pin
Now, can I type echo 328, 340, 339, 338 > export in order?
You donāt need to do anything to use the SPI interface once the overlay is loaded.
You just need to write some software to talk with whatever is connected.
1 Like
Because the source code was written as below, I tried to change the setting related to the GPIO pin number mentioned above.
#define SS_PIN 328 // SPI SS(Chip Select) GPIO pin number
#define MOSI_PIN 339
#define MISO_PIN 340
#define SCK_PIN 338
int main() {
// SS pin setting
int ss_gpio_fd;
char ss_gpio_path[64];
// SS pin open
snprintf(ss_gpio_path, sizeof(ss_gpio_path), ā/sys/class/gpio/gpio%d/valueā, SS_PIN);
ss_gpio_fd = open(ss_gpio_path, O_WRONLY);
// Set SS pin as output
write(ss_gpio_fd, āoutā, 3); // or āinā
// MOSI pin setting
int mosi_gpio_fd;
char mosi_gpio_path[64];
// MOSI pin open
snprintf(mosi_gpio_path, sizeof(mosi_gpio_path), ā/sys/class/gpio/gpio%d/valueā, MOSI_PIN);
mosi_gpio_fd = open(mosi_gpio_path, O_WRONLY);
// Set MOSI pin as output
write(mosi_gpio_fd, āoutā, 3);
// MOSI pin close
close(mosi_gpio_fd);
// MISO pin setting
int miso_gpio_fd;
char miso_gpio_path[64];
// MISO pin open
snprintf(miso_gpio_path, sizeof(miso_gpio_path), ā/sys/class/gpio/gpio%d/valueā, MISO_PIN);
miso_gpio_fd = open(miso_gpio_path, O_WRONLY);
// Set MISO pin as input
write(miso_gpio_fd, āinā, 2);
// MISO pin close
close(miso_gpio_fd);
// SCK pin setting
int sck_gpio_fd;
char sck_gpio_path[64];
// SCK pin open
snprintf(sck_gpio_path, sizeof(sck_gpio_path), ā/sys/class/gpio/gpio%d/valueā, SCK_PIN);
sck_gpio_fd = open(sck_gpio_path, O_WRONLY);
// Set SCK pin as output
write(sck_gpio_fd, āoutā, 3);
// SCK pin close
close(sck_gpio_fd);
// SPI communication initialization
if (SpiInit() != 0) {
return -1;
}
// MFRC522 initialization
MFRC522Init();
// UART communication initialization
if (UartInit() != 0) {
return -1;
}
uint8_t nuidPICC[4] = {0}; // Save old card UID
while (1) {
// If the card is recognized, move on to the next, otherwise do not run any further.
if (!PiccIsNewCardPresent())
continue;
// If the ID has been read, it goes to the next one, otherwise it doesn't run any further.
if (!PiccReadCardSerial(nuidPICC))
continue;
// write value to SS pin (set to 0)
write(ss_gpio_fd, "0", 1); // low
printf("PICC type: ");
// Read the type of card
uint8_t piccType = PiccGetType(nuidPICC[0]);
// print monitor
printf("%s\n", PiccGetTypeName(piccType));
// Check if it is a MIFARE method and return otherwise
if (piccType != MFRC522_PICC_TYPE_MIFARE_MINI &&
piccType != MFRC522_PICC_TYPE_MIFARE_1K &&
piccType != MFRC522_PICC_TYPE_MIFARE_4K) {
printf("Your tag is not of type MIFARE Classic.\n");
continue;
}
// If it is different from the RF card recognized just before. That is, to prevent duplicate card detection.
if (nuidPICC[0] != nuidPICC[0] ||
nuidPICC[1] != nuidPICC[1] ||
nuidPICC[2] != nuidPICC[2] ||
nuidPICC[3] != nuidPICC[3]) {
printf("A new card has been detected.\n");
// ID save
memcpy(nuidPICC, nuidPICC, sizeof(nuidPICC));
// print monitor
printf("The NUID tag is:\n");
printf("In hex: ");
// Convert to hexadecimal and output
printHex(nuidPICC, sizeof(nuidPICC));
printf("\n");
// Send card information to PC via UART
char uartData[9];
snprintf(uartData, sizeof(uartData), "%02X%02X%02X%02X\n", nuidPICC[0], nuidPICC[1], nuidPICC[2], nuidPICC[3]);
WriteUidUart(uartData);
}
// write value to SS pin (set to 1)
write(ss_gpio_fd, "1", 1); // high
// PICC end
usleep(100000);
}
close(spi_fd);
close(uart_fd);
// SS pin close
close(ss_gpio_fd);
return 0;
}
Well that is not going to work on the BBAI-64.
Not unless the code is trying to do bit banging to wrtie to the SPI device, in which case you donāt want to enable the SPI with the overlay. But that would be very slow.
Where did that code come from ?
How is the code writing to the SPI port ?
Assuming you are using SPIDEV you donāt need to control the SS pin (cs pin) it is done automatically by the driver. The only reason you might want to is if you need to break the data into multiple chunks with multip SPIDEV calls and keep the CS low during that time, or you need to use an I/O pin that isnāt on the SPI peripheral.
1 Like
This is the code I wrote myself for SPI communication between RFID and BBAI-64 boards and UART communication between boards and PCs.
The method of writing data to the SPI port overlaid the BONE-SPI0_0.dtbo file.
In addition, I will add several functions written in the main function.
#include <stdio.h>
#include <string.h>
#include <stdint.h>
#include <stdint.h>
#include <stdlib.h>
#include <unistd.h>
#include <fcntl.h>
#include <sys/ioctl.h>
#include <linux/spi/spidev.h>
#include <linux/gpio.h>
#include <termios.h>
#define SPI_DEVICE ā/dev/spidev0.0ā // SPI device path(X: bus number, Y: device number)
#define UART_DEVICE ā/dev/ttyS0ā // UART device path
#define SS_PIN 328 // SPI SS(Chip Select) GPIO pin number
#define MOSI_PIN 339
#define MISO_PIN 340
#define SCK_PIN 338
#define MFRC522_PICC_TYPE_MIFARE_MINI 0x09
#define MFRC522_PICC_TYPE_MIFARE_1K 0x04
#define MFRC522_PICC_TYPE_MIFARE_4K 0x02
int spi_fd;
int gpio_fd;
int uart_fd;
// SPI communication initialization
int SpiInit() {
spi_fd = open(SPI_DEVICE, O_RDWR);
// SPI mode setting
uint8_t mode = SPI_MODE_0;
ioctl(spi_fd, SPI_IOC_WR_MODE, &mode);
// Setting the Maximum Transmission rate (1MHz)
uint32_t speed = 1000000;
ioctl(spi_fd, SPI_IOC_WR_MAX_SPEED_HZ, &speed);
return 0;
}
// Send and receive SPI data
int SpiTransfer(uint8_t* tx_data, uint8_t* rx_data, int len) {
struct spi_ioc_transfer spi_transfer = {
.tx_buf = (unsigned long)tx_data,
.rx_buf = (unsigned long)rx_data,
.len = len,
.delay_usecs = 0,
.speed_hz = 1000000,
.bits_per_word = 8,
};
if (ioctl(spi_fd, SPI_IOC_MESSAGE(1), &spi_transfer) < 0) {
printf(āSPI transfer error\nā);
return -1;
}
return 0;
}
void MFRC522Init() {
uint8_t tx_data[] = {0x0F}; // Data value for sending softreset commands to MFRC522
uint8_t rx_data[sizeof(tx_data)];
if (SpiTransfer(tx_data, rx_data, sizeof(tx_data)) < 0) {
printf("Failed to send SPI message\n");
return;
}
usleep(5000); // Hold on a second
}
// Check if the Card Exists
int PiccIsNewCardPresent() {
uint8_t tx_data[] = {0x52}; // Data pattern value for sending the function to MFRC522, 0x52 : find all the cards antenna area
uint8_t rx_data[sizeof(tx_data)];
memset(rx_data, 0, sizeof(rx_data));
if (SpiTransfer(tx_data, rx_data, sizeof(tx_data)) < 0) {
printf(āFailed to transfer data\nā);
return -1;
}
return rx_data[1];
}
// Read card UID information
int PiccReadCardSerial(uint8_t* uid) {
uint8_t tx_data[] = {0x93}; // Data pattern value for sending the function to MFRC522, 0x93 : election card
uint8_t rx_data[sizeof(tx_data)];
memset(rx_data, 0, sizeof(rx_data));
if (SpiTransfer(tx_data, rx_data, sizeof(tx_data)) < 0) {
printf(āFailed to transfer data\nā);
return -1;
}
memcpy(uid, &rx_data[1], 4);
return 0;
}
// Get card type
uint8_t PiccGetType(uint8_t sak) {
return sak & 0x7F;
}
// Get card type name
const char* PiccGetTypeName(uint8_t piccType) {
switch (piccType) {
case MFRC522_PICC_TYPE_MIFARE_MINI:
return āMIFARE Miniā;
case MFRC522_PICC_TYPE_MIFARE_1K:
return āMIFARE 1Kā;
case MFRC522_PICC_TYPE_MIFARE_4K:
return āMIFARE 4Kā;
default:
return āUnknownā;
}
}
// Convert to hexadecimal and output
void printHex(uint8_t* data, uint8_t length) {
for (uint8_t i = 0; i < length; i++) {
printf(ā%02Xā, data[i]);
}
}
// UART initialization
int UartInit() {
uart_fd = open(UART_DEVICE, O_RDWR | O_NOCTTY);
if (uart_fd < 0) {
printf(āFailed to open UART\nā);
return -1;
}
struct termios options;
tcgetattr(uart_fd, &options); // import current setting
// Set transfer rate (9600 bps)
cfsetispeed(&options, B9600);
cfsetospeed(&options, B9600);
// Set data bits, parity bits, and stop bits
options.c_cflag &= ~PARENB;
options.c_cflag &= ~CSTOPB;
options.c_cflag &= ~CSIZE;
options.c_cflag |= CS8;
// control option setting
// options.c_cflag &= ~CRTSCTS;
options.c_cflag |= CREAD | CLOCAL;
options.c_iflag &= ~(IXON | IXOFF | IXANY);
options.c_lflag &= ~(ICANON | ECHO | ECHOE | ISIG);
options.c_oflag &= ~OPOST;
tcsetattr(uart_fd, TCSANOW, &options); // apply new settings to uart_fd
return 0;
}
// To transmit PC data using UART.
void WriteUidUart(const char* data) {
write(uart_fd, data, strlen(data));
}
Ok so you are using spidev and not bit banging.
You donāt need the exports. All that will do is try to export the pin as a gpio pin.
You also probably donāt need to control the cs pin manually.
The spi hardware will drive it low at the start of the transmit and then pull it high at the end. If memory serves me right there is some sort of control for how the cs works when writing/reading multiple transfers in 1 ioctl command.
If you find you have to manually control the cs pin, you will either need to modify the devicetree, or perhaps the easiest option would be to configure an unused gpio pin and connect the cs to that pin.
1 Like
Does it mean that I only need to register gpio pins with echo 328, 340, 339, 338 > export?
Also, even though the gpio-338 pin is set as BOOTMODE 1, does the registered gpio automatically act as spi6_cs0, spi6_d1, spi6_d0, spi6_clk if the BONE-SPI0_0.dbo overlay and gpio pin are registered regardless?
No you do not need to export anything.
The devicetree sets the pin into the correct mode.
Then, as mentioned above, it seems that it can be changed simply by modifying the device tree.
/dts-v1/;
/plugin/;
... same ...
&bone_spi_0 {
/* tested with: sudo ./spidev_test -v --device /dev/spidev0.0 /
pinctrl-names = ādefaultā;
pinctrl-0 = <
&P9_17A_spi_pin / spi6_cs0 /
&P9_22A_spi_pin / spi6_clk /
&P9_21A_spi_pin / spi6_d0 /
&P9_18A_spi_pin / spi6_d1 */
>;
ti,spi-num-cs = <1>;
ti,pindir-d0-out-d1-in;
... same ...
};
I assigned the role (A or B) indicated by each pin number.
Iāll try overlaying this.
No, why are you trying to change the overlay. It already exists. It is correct.
Also what you have probably would not work as all of those header pins are connected to 2 different pads on the MCU. That is why they are labeled A and B.
If you are going to configure one of these, you also need to configure the unused pad as a GPIO input.
You can see this by looking at the file k3-j721e-beagleboneai64-bone-buses.dtsi
This has a big bunch of macros to describe the pins so can be a little hard to understand exactly what is going on.
#define BONE_PIN(XX,ZZ,QQ) \
XX##_##ZZ##_pin: pinmux_##XX##_##ZZ##_pin { pinctrl-single,pins = < QQ >; };
Anyway if you look at the macro that generates the SPI pinctrls you will see it configures both A and B. The B pad is set to a GPIO pin in input mode.
BONE-SPI0_0.dts
--------------------------
&bone_spi_0 {
/* tested with: sudo ./spidev_test -v --device /dev/spidev0.0 */
pinctrl-names = "default";
pinctrl-0 = <
&P9_17_spi_pin /* spi6_cs0 */
&P9_22_spi_pin /* spi6_clk */
&P9_21_spi_pin /* spi6_d0 */
&P9_18_spi_pin /* spi6_d1 */
>;
k3-j721e-beagleboneai64-bone-buses.dtsi
-------------------------------------------------------------
BONE_PIN(P9_17, spi, P9_17A(PIN_OUTPUT, 4) P9_17B(PIN_INPUT, 7)) /* spi6_cs0 */
BONE_PIN(P9_18, spi, P9_18A(PIN_INPUT, 4) P9_18B(PIN_INPUT, 7)) /* spi6_d1 (tested PIN_INPUT) */
BONE_PIN(P9_21, spi, P9_21A(PIN_OUTPUT, 4) P9_21B(PIN_INPUT, 7)) /* spi6_d0 */
BONE_PIN(P9_22, spi, P9_22A(PIN_OUTPUT, 4) P9_22B(PIN_INPUT, 7)) /* spi6_clk */
Because, even though BONE-SPI0_0.dtbo was overlaid and the card was touched, no action occurred between the RFID and the BBAI-64 board.
So I thought that it didnāt work because the gpio pin number was not registered in the /sys/class/gpio path.
Ok, so we need to check that the overlay was actually loaded.
root@BeagleBone:/# ls /proc/device-tree/chosen/overlays/
BONE-SPI0_0.kernel name
This should show what devicetrees have been loaded.
Also run
root@BeagleBone:/# lsmod | grep spidev
spidev 24576 0
To make sure the spidev driver has been loaded.
As a result of executing the command root@BeagleBone:/# ls /proc/device-tree/chosen/overlays/,
BONE-SPI0_0.kernel name
The above files exist.
However, the file according to the command below does not exist.
root@BeagleBone:/# lsmod | grep spidev
spidev 24576 0
Ok edit /etc/modules-load.d/modules.conf and add spidev to the end of the file.
this will make sure the driver is loaded on boot.
you can also do
modprobe spidev
to load the driver without having to reboot.
Check with lsmod | grep spidev to make sure it has been loaded.
yes! Done!!
as you said,
root@BeagleBone:/# lsmod | grep spidev
BONE-SPI0_0.kernel name
root@BeagleBone:/# ls /proc/device-tree/chosen/overlays/
spidev 24576 0
I ran the command and it came out like above:
Are there any next steps?
Well the spi bus should work. The rest will be down to your software
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