How to synchronize ADC sampling clock ?

Hi,
how to synchronize ADC sampling clock (CLK_M_OSC, in AM335x manual, page 3731) with external 1PPS source or others?
I used PTP to synchronize system clock in the kernel before, however, the jitter is about 30us (but I need a jitter with accuracy under 1us.).
So I want to synchronize ADC sampling clock(24MHz), Is there any way to synchronize it ? Is the clock of CLK_M_OSC be adjustable?
Thanks.

Hi,
how to synchronize ADC sampling clock (CLK_M_OSC, in AM335x manual, page 3731) with external 1PPS source or others?
I used PTP to synchronize system clock in the kernel before, however, the jitter is about 30us (but I need a jitter with accuracy under 1us.).
So I want to synchronize ADC sampling clock(24MHz), Is there any way to synchronize it ? Is the clock of CLK_M_OSC be adjustable?
Thanks.

There is no way to do this with Linux because the interrupt latency on the standard kernel is probably somewhere between 100uS and 1mS. If you want 1uS accuracy, then I suggest you use the PRU.

Regards,
John

Hi,

if you control the ADC from the PRU, you can use the ADC in single-acquisition mode and perform a new acquisition every 200 PRU cycles (every microsecond) for example (or whatever repetition rate you want), and therefore use the 200 MHz PRU clock as a low-jitter timer. This way you can have jitter values well below one microsecond. You should also be able to synchronize the PRU with an external clock on one of its input pins leading to the r31 register if that is still needed.

There should probably be a residual timing jitter of maximally 1/24MHz (ca. 42ns) because (as far as i know, but im not sure) the 24 MHz ADC sampling clock is not intrinsically synchronized with the 200 MHz PRU clock, so once the PRU launches a new acquisition, it won’t take place before the ADC clock starts a new cycle. I did not find any documentation on how the PRU and ADC clock signals are derived in the hardware, that is if they come from the master clock or not, but i did experimentally observe a jitter of a few percent of a microsecond.

If you want I can send you some code examples.

Lenny

Hi,

if you control the ADC from the PRU, you can use the ADC in single-acquisition mode and perform a new acquisition every 200 PRU cycles (every microsecond) for example (or whatever repetition rate you want), and therefore use the 200 MHz PRU clock as a low-jitter timer. This way you can have jitter values well below one microsecond. You should also be able to synchronize the PRU with an external clock on one of its input pins leading to the r31 register if that is still needed.

There should probably be a residual timing jitter of maximally 1/24MHz (ca. 42ns) because (as far as i know, but im not sure) the 24 MHz ADC sampling clock is not intrinsically synchronized with the 200 MHz PRU clock, so once the PRU launches a new acquisition, it won’t take place before the ADC clock starts a new cycle. I did not find any documentation on how the PRU and ADC clock signals are derived in the hardware, that is if they come from the master clock or not, but i did experimentally observe a jitter of a few percent of a microsecond.

If you want I can send you some code examples.

That sounds like a good solutions. Also, you could use a 1MHz timer which you can synchronize to the PTP clock and then just average the ADC samples received since the last clock interrupt.

Regards,
John

Hello, Lenny,
your solution is good, thanks. Here is another question : is it capable of synchronizing “multiple” ADC channels at one time ?

I have read ADC driver limitation from TI :
http://processors.wiki.ti.com/index.php/AM335x_ADC_Driver's_Guide#ADC_Driver_Limitations

and you said that I can use the ADC in single-acquisition mode. → Is it capable of synchronizing “multiple channels” at one time? (because I need to sample three-phase current and voltage signal, so the sum of them are 6 channels.)

I am not sure “single-acquisition” is limitation of hardware (ADC) naturally or just limitation of driver function?
If I use single-acquisition mode, then I need to consider the effect of conversion time between one channel and another channel.

Finally, If I could, please send your sample code for me to my gmail. Thanks!

Hi, John,
could you specify which 1MHz timer ? I just know 24MHz clock for ADC…
About synchronization, I will try to synchronize ADC(with PRU as Lenny said) to PTP clock (on CPTS, common platform time sync) rather than kernel system clock.
Do you have experience handling CPTS? I am not sure if CPTS driver has ability of triggering other hardware unit (software trigger), and what its accuracy of synchronization is.

Thanks.

john3909於 2014年7月24日星期四UTC+8上午1時43分56秒寫道:

Hi, John,
could you specify which 1MHz timer ? I just know 24MHz clock for ADC…
About synchronization, I will try to synchronize ADC(with PRU as Lenny said) to PTP clock (on CPTS, common platform time sync) rather than kernel system clock.
Do you have experience handling CPTS? I am not sure if CPTS driver has ability of triggering other hardware unit (software trigger), and what its accuracy of synchronization is.

In my case, this is a 1MHz external clock that is synchronized to the 1pps of a GPS using a very accurate VCO and stable. CPTS is just TI’s code that enables compliance with the IEEE1588 standard.

Regards,
John

Hi, John,
could you specify which 1MHz timer ? I just know 24MHz clock for ADC…
About synchronization, I will try to synchronize ADC(with PRU as Lenny said) to PTP clock (on CPTS, common platform time sync) rather than kernel system clock.
Do you have experience handling CPTS? I am not sure if CPTS driver has ability of triggering other hardware unit (software trigger), and what its accuracy of synchronization is.

Have you looked at this:

http://processors.wiki.ti.com/index.php/TI81XX_PSP_Ethernet_Switch_User_Guide#IEEE_1588.2F802.1AS_PTP_Support

Regards,
John

Hi,
I never tried to read several ADC channels “simultaneously”, but as far as I understand the TRM section on this, there is really only one hardware ADC witht multiplexer to make 8 channels. One acquisition takes at least 15 ADC clock cycles (625ns), that is for 6 channels, you would have to read one value after the other, giving you a 625 ns delay between subsequent values and a maximum 6-channel-samling rate of 1/3750ns = roughly 250kHz. As said above, jitter won’t be too much of a problem here. Since the readout of the FIFO buffer also induces some delay, you should more realistically consider 200-250 kHz.
So if you can tolerate the delay of digitalization of the different analog inputs, the integrated ADC will work, otherwise you should consider using an external ADC.

Hi,
I never tried to read several ADC channels “simultaneously”, but as far as I understand the TRM section on this, there is really only one hardware ADC witht multiplexer to make 8 channels. One acquisition takes at least 15 ADC clock cycles (625ns), that is for 6 channels, you would have to read one value after the other, giving you a 625 ns delay between subsequent values and a maximum 6-channel-samling rate of 1/3750ns = roughly 250kHz. As said above, jitter won’t be too much of a problem here. Since the readout of the FIFO buffer also induces some delay, you should more realistically consider 200-250 kHz.
So if you can tolerate the delay of digitalization of the different analog inputs, the integrated ADC will work, otherwise you should consider using an external ADC.

You could also use a small FPGA to do the data ack, time synchronization and time stamp the buffer like they do in ZIO.

http://www.ohwr.org/projects/zio

It is also possible to do this with IIO and there are examples on Analog Devices website for doing high speed data ack.

https://wiki.analog.com/resources/fpga/xilinx/fmc/ad-fmcjesdadc1-ebz

Regards,
John