IP Cores on BeagleV -Fire

Good day! I am migrating from ICICLE KIT to BeagleV. I would appreciate if someone has an introduction of the Libero Project of the BeagleV-Fire and how can I apply IP Cores to the Board and run them.

I really appreciate your help!


The Libero project is integrated as part of the BeagleV-Fire build system: BeagleV-Fire / Gateware ยท GitLab.
If you are familiar with the Icicle Kit reference design think of the BeagleV-Fire build system as a python script that keep your Libero Design, HSS and MSS Configuration consistent. Avoiding these to get out of synch.
The Libero/FPGA design TCL script for BEagleV-Fire is very similar to the Icicle Kit reference design TCL script. So you should be able to easily find your way around it.

Thank you for the information! Still is very hard in Libero to make a new IP Core from scratch! I will try to develop it on the beagleV-Fire!

Really! I appreciate your time taken to answer here!

Hey! I would like to ask another thing, is it possible to use VHDL codes in the Gateware? I have only seen Verilog codes, and I want to implement this VHDL codes that I already have. Is there a way to implement the VHDL codes into the fpga-custom-design?

Yes, VHDL can be used. Please check-out this video: https://www.youtube.com/watch?v=mpS3sJWwJAQ

Thank you very much for the info! I really appreciate it!