Is there a way to decrease the interval between bytes during an SPI transfer?

Hello all,

I have a Beaglebone Black reading from an FPGA over SPI. I’m trying to get the interface as fast as possible. I can set the clock rate fine and am running well at 24MHz. In looking on an oscilloscope, there is a gap of ~1us between each byte when although the bit rate is 24MHz. Is there a setting that can be changed to minimize the gap? Is there a parameter for spidev that can be adjusted?

I’m using Debian 3.8.13-bone70 and the Adafruit BBIO library with Python. Also, I’m using a xfer2 where the select line stays low for the entire transfer.


Hi Dave,

Does changing the clock frequency have an impact on latency between bytes ? I’ve read that spidev should be able to handle 48Mhz. But if increasing the clock frequency does not help, or gives diminishing returns. You may be bumping up against the limitation of running such an application from user space. In which case, you may need to change to a different language( native compiled binary versus interpreted script ), or even move to using a PRU or two to help offload the processor.

Granted 8Mbit/s does not seem terribly fast . . .


Thanks for the reply. Changing the frequency has no effect. Yes, I’ve been able to run the clock at 48MHz and below (24,12,etc.). All clock settings have the same delay between bytes.

I’ve looked at the Adafruit Python library source and see that there is a parameter “delay_us” that may apply but I’m not sure. It is set to 0 in the library. (It doesn’t have a function brought out to change it anyway) I also looked at the Sitara TRM and didn’t see anything that would indicate it’s a register setup or processor setting.

I’m thinking it’s buried in a Linux driver somewhere, but I’m not sure where to look or if it is easily fixed.