I have an issue with a custom board, based on BeagleBone Black (BEAGLEBK) and AM3359 ICS (TMDSICE3359) design.
This board has 3 Ethernet Ports:
Port1: on CPSW MII1 with PHY address 0 → eth0
Port2: on PRU0 with PHY address 1 → eth1
Port3: on PRU1 with PHY address 0 → eth2
According to http://processors.wiki.ti.com/index.php/PRU-ICSS_Ethernet I’m going to utilize all 3 ports on linux.
Following basics seems to work:
- The PRU-ICSS firmware binaries are loaded:
Hi, are the power sequence /reset timing on the 3 ports correct?
Are you talking about the PHYs?
The normal way should be (as far as I understand) to cede the reset-timing to the prueth driver. But if I do so (define reset-gpios and reset-delay-us in pruss-mdio node), the PHY reset is never released.
So I handle the PHY-reset manually via GPIO access within a script. (The same script works fine if I use the PRU ports with EtherCAT or ProfiNet firmware)
Btw. the CPSW ethernet port (eth0) works fine, if I didn’t mention it clearly enough.