MCSPI TX works fine, but RX all zeros

GoogleGroups
21

Many thanks. It's working indeed. As the same time, it seems that
Philip has made some progress on the SPI itself,

Grégoire

22

About this tread, Mr. Balister has made some progress on this issue.
http://groups.google.com/group/beagleboard/browse_thread/thread/42988f0e14db0f01/816397901ec999c4?lnk=gst&q=Balister+#816397901ec999c4

yuchih

23

Hi, guy.

I had had the same problem.
But I solved it.

The problem was very simple.
We have to set “RXACTIVE” bit to CLK Pin’s “Conrol Module Resiters(PINMUX)”.

So dts file is follows
spi0_pins: pinmux_spi0_pins {
pinctrl-single,pins = <
0x150 ( PIN_INPUT_PULLUP | MUX_MODE0 ) /* (P23) spi0_sclk.spi0_sclk /
0x154 ( PIN_INPUT_PULLUP | MUX_MODE0 ) / (T22) spi0_d0.spi0_d0 /
0x158 ( PIN_OUTPUT_PULLUP | MUX_MODE0 ) / (T21) spi0_d1.spi0_d1 /
0x15c ( PIN_OUTPUT_PULLUP | MUX_MODE0 ) / (T20) spi0_cs0.spi0_cs0 */

;
};

And, we can see in “Technical Reference Manual” 26.2.3.
It is said “SPI serial clock (output when master, input when slave)”
And it also said “(1) This output signal is also used as a re-timing input. The associated CONF___RXACTIVE bit for the output clock must be set to 1 to enable the clock input back to the module.”

24

Many thanks ksuzik,

I had the same issue with mcspi0 as master. Setting SCLK to input by default solved it.