I’m planning on reading the PRU IO inputs a large number of consecutive times and move them (eventually) to DDR space. As part of my code, I tried one instruction like:
MVIW *r0.w0++, r31.w0
which from section 5.3.4.2.3 Move Register File Indirect (MVIx)
of the PRU reference manual seems correct to me; however when trying to compile using PASM_2, I get the error message:
PRU Assembler Version 0.86
Copyright © 2005-2013 by Texas Instruments Inc.
logic_pru1.p(42) Error: This form of MVIx illegal with specified core version
Pass 1 : 1 Error(s), 0 Warning(s)
I have searched the PRU and the AM335X manuals and I can’t find any sections stating the AM3358 does not support MVIx instructions.
Does anyone have any experience here? Thanks.
Bit_Pusher
Keep reading the PRU Reference Guide. Specifically, section 5.3.4.2.3.1
"Standard PRU Core Support" which tells you this is implemented as a
pseudo-op and only register to register moves are supported.
If you're interested in moving data from the PRU to the ARM side
quickly, check out the BeagleLogic project (from last year's Google
Summer Of Code):
https://github.com/abhishek-kakkar/BeagleLogic/wiki
...this is about as optimized as you can get for moving data from the
PRU to the Linux ARM side, and everything's already written for you
(including the kernel mode driver necessary to get the highest speeds).
Charles, thank you for getting back to me. Could you tell me which Pru Reference
Guide you are quoting. The one I have is: SPRUHF8A, revised June 2013, and
section 5.3.4.2.3.1 does not have the words “Standard PRU Core Support” in it.
The reference I have has examples of indirect reads followed by examples of indirect
writes where in each case the semantics r1.b0 (for example, used in the first indirect write example) indicates the lowest significant byte of register r1 contains the address of the register that should be written, in the example, r1 contains 8, so the register written into in the example is register 2 which starts at byte 8. and in this example, since a single byte is being written, register 2 ends up containing 0x00000004, the least significant byte of r3. In the reference I am reading, the word “pseudo” does not occur in section 5.3.4.2.3.1; do you have a newer reference? My understanding is the whole point of the MVIx op codes are to allow for first indirect addressing (where the specified register contains the address of the register to be either read from or written to, as indicated by typing '’ just in front of the register name, and that both read and written registers can contain ‘*’, that is can be indirect) and also to allow for auto incrementing and/or decrementing; it’s the auto incrementing I really want otherwise I have to use a number of instructions to realize the equivalent. I can only guess that the reference you are quoting from is different than the one I have; could you give me a link to the reference you are quoting from? Irrespective, this still does not explain the error message “This form of MVIx illegal with specified core version”; I can not find anywhere which cores support MVIx and which do not. In the meantime, I will read the example you suggest.Thanks again.
-Bit_Pusher
Charles, thank you for getting back to me. Could you tell me which Pru
Reference
Guide you are quoting. The one I have is: SPRUHF8A, revised June 2013, and
section 5.3.4.2.3.1 does not have the words "Standard PRU Core Support" in
it.
SPRUHF8–May 2012
In general, the older PRU documentation has less stuff redacted. 
The reference I have has examples of indirect reads followed by examples of
indirect
writes where in each case the semantics *r1.b0 (for example, used in the
first indirect write example) indicates the lowest significant byte of
register r1 contains the address of the register that should be written, in
the example, r1 contains 8, so the register written into in the example is
register 2 which starts at byte 8. and in this example, since a single byte
is being written, register 2 ends up containing 0x00000004, the least
significant byte of r3. In the reference I am reading, the word "pseudo"
does not occur in section 5.3.4.2.3.1; do you have a newer reference? My
understanding is the whole point of the MVIx op codes are to allow for
first indirect addressing (where the specified register contains the
address of the register to be either read from or written to, as indicated
by typing '*' just in front of the register name, and that both read and
written registers can contain '*', that is can be indirect) and also to
allow for auto incrementing and/or decrementing; it's the auto incrementing
I really want otherwise I have to use a number of instructions to realize
the equivalent. I can only guess that the reference you are quoting from is
different than the one I have; could you give me a link to the reference
you are quoting from? Irrespective, this still does not explain the error
message "This form of MVIx illegal with specified core version"; I can not
find anywhere which cores support MVIx and which do not. In the meantime, I
will read the example you suggest.Thanks again.
Yes, read through the BeagleBone logic analyzer code. It's been tweaked
to run as fast as possible, and is known to work.
Eventually tracked it down to not having -V3 flags in pasm compile comand (they were missing from Makefile originally copied from TI examples).