pickard@gmail.com said the following on 03/03/2009 06:31 PM:
Hi,
My name is Tom Pickard and I'm working on using the Beagle Board to
run some SDR (not GNURadio) applications. I've been experimenting with
running Angstrom from an SD card, but now I'm interested in moving all
the code into NAND since we aren't too hot on using SD for our system.
Following the guide at BeagleBoardNAND - eLinux.org , I loaded x-
loader, u-boot and the kernel into NAND from the u-boot prompt. I am
still working on getting the file system right, but what I'm wondering
is how the ECC stuff works with NAND. I know that you specify HW/SW
ECC when writing the NAND from u-boot, but what about when writing
from within Linux?
How robust is the HW/SW ECC?
Thanks for your help.
Lets get some concepts:
a) What is ECC? hamming code and it can detect upto 2 bit errors and
correct up to 1 bit errors.
b) on NAND flash, the geometry is as follows:
1 device is divided into n blocks
1 block is divided into m pages
and 1 page is divided into data area and spare area (a.k.a out of band
or oob area)
Now, for 2048 byte data area on NAND,
S/w ecc as implemented in linux and u-boot is for 256 byte. This
essentially means we have 1 bit correction and 2 bit detection for every
256 bytes of data.
h/w ecc as implemented in GPMC is for 512 byes: this means 1 bit
correction and 2 bit detection for every 512 bytes of data.
As obvious, for 2048 bytes of data, s/w ecc can detect and correct upto
8 bits.. detect upto 16bits errors, while h/w ecc would probably do half
as much.
Robustness wise, s/w ecc does twice as good as h/w ecc.. Now to the catch..
a) performance: s/w ecc is essentially a cpu intensive operation while
GPMC in h/w ecc does it on the fly
b) size: the number of bytes required to store the ecc data for s/w ecc
is double the number of bytes required for h/w ecc
So, for a given application, you'd need to choose the correct balance.
Hope this helped..
Regards,
Nishanth Menon