New Cape LCD timing problems

I’m building a new cape with a 5.7" LCD on it. I’ve got the BeagleBone Black recognizing the EEPROM and loading the .dtbo file. The UART2 connection I’m also using is being initialized.

The problem that I’m having is getting the LCD timing to work out correctly. The 4.3" display cape is 480x272 pixels and the 7" display cape is 800x480. The 5.7" display that I’m using is 640x480 pixels. If I set the timing for the LCD display to the values used by either the 4.3" LCD cape or the 7" LCD cape the signals on the pins look like they should. If I set the LCD timing to the values necessary for my display or any combination that would produce 640x480 then the signals that come out look like they have been divided by about 64, i.e. the horizontal sync rate is 488Hz instead of 31.468KHz and the vertical sync rate is about 1 second instead of 60Hz, the pixel clock is only 390KHz but the width of the positive pulse is the same as what it would be for a 25.175MHz clock which is the frequency for 640x480 display.

Here is the relevant portion of the dts file:


panel {
compatible = “tilcdc,panel”;
pinctrl-names = “default”;
pinctrl-0 = <&bbb_lcd_pins>;
panel-info {
ac-bias = <255>;
ac-bias-intrpt = <0>;
dma-burst-sz = <16>;
bpp = <16>;
fdd = <0x80>;
tft-alt-mode = <0>;
stn-565-mode = <0>;
mono-8bit-mode = <0>;
sync-edge = <0>;
sync-ctrl = <1>;
raster-order = <0>;
fifo-th = <0>;
display-timings {
native-mode = <&timing0>;
timing0: 640x480 {
hactive = <640>; /* active pixels /
vactive = <480>; /
active lines /
hback-porch = <48>; /
in pixels /
hfront-porch = <16>;
hsync-len = <96>;
vback-porch = <33>; /
in lines /
vfront-porch = <10>;
vsync-len = <2>;
clock-frequency = <25175000>;
hsync-active = <0>; /
0=low, 1=high, 2=ignored */
vsync-active = <0>;
timing1: 480x272 {
hactive = <480>;
vactive = <272>;
hback-porch = <44>;
hfront-porch = <9>;
hsync-len = <5>;
vback-porch = <13>;
vfront-porch = <4>;
vsync-len = <10>;
clock-frequency = <9000000>;
hsync-active = <0>;
vsync-active = <0>;
timing2: 800x480 {
hactive = <800>;
vactive = <480>;
hback-porch = <40>;
hfront-porch = <40>;
hsync-len = <48>;
vback-porch = <30>;
vfront-porch = <13>;
vsync-len = <3>;
clock-frequency = <30000000>;
hsync-active = <0>;
vsync-active = <0>;


The timing0 section is actually what is used for a 640x480 VGA monitor, but it is within the specs for the LCD that I’m using, I have tried other combinations of vertical and horizontal numbers that add up to the total of 800 total pixels per line and 525 total lines per vertical sync and I get the same problem

The timing1 section is from the LCD4 cape, the timing2 section is from the LCD7 cape.

I’ve also tried changing the name of the sections, I put the 480x272 timing values into the 640x480 section and the display controller put out the correct timing for a 480x272 display, I also put the 640x480 timing values into the 480x272 section and the LCD controller put out the incorrect signals. I did this to make sure that there wasn’t some other driver issue that was based on the name that I didn’t understand.

At this point I’m confused as to why the LCD controller is acting the way that it is. Any help that will shed some light on what is happening would be greatly appreciated. If there is a better place to ask about these kinds of problems that would be appreciated also.

It appears to be a problem with the pixel clock divider. I copied the 800x480 parameters and then changed the pixel clock to 25.175MHZ and I got the same behavior as the 640x480 parameters. Then I changed the clock to 25MHz even and I got the correct pixel clock out. 25.1 MHZ doesn’t work, but 25.2MHz does work. So there appears to be some frequencies that the pixel clock divider can’t produce and it messes everything up.

I’m going to continue trying to get my board up and running using the 25.2MHz pixel clock. This is a bit fast but hopefully should still work.