Omap3 Performance Counters

Nils_Pipenbrinck1 · November 8, 2009, 4:18pm

Hi folks.

Yesterday I've tried to get access to the Omap3 performance counters.

To enable usermode access I wrote a minimal kernel-module that toggles
the performance counter user-mode access flag in the coprocessor. The
module worked out of the box.

I'm now able to read the cycle counter register. I can reset all
event-counters, read and write to them, setup events and so on without
problems. However, no matter what I program into the event-registers,
the counter-register never increase.

I found some old posts on this list regarding the same issue, so I
wonder if someone has solved the problem in the meantime.

Btw: I'm running my tests on a rev. B4 beagleboard which as far as I
know has very early silicon. Is it possible that the performance
counters are simply not functional with this revision?

Cheers,
Nils

Bill_Gatliff · November 9, 2009, 1:32pm

np wrote:

Hi folks.

Yesterday I've tried to get access to the Omap3 performance counters.

To enable usermode access I wrote a minimal kernel-module that toggles
the performance counter user-mode access flag in the coprocessor. The
module worked out of the box.

I'm now able to read the cycle counter register. I can reset all
event-counters, read and write to them, setup events and so on without
problems. However, no matter what I program into the event-registers,
the counter-register never increase.

I found some old posts on this list regarding the same issue, so I
wonder if someone has solved the problem in the meantime.

Btw: I'm running my tests on a rev. B4 beagleboard which as far as I
know has very early silicon. Is it possible that the performance
counters are simply not functional with this revision?

Are you declaring your pointers as volatile? Maybe gcc is optimizing
out your reads from the counter register?

b.g.

Nils_Pipenbrinck1 · November 9, 2009, 2:51pm

Bill Gatliff wrote:

Are you declaring your pointers as volatile? Maybe gcc is optimizing
out your reads from the counter register?

Hi Bill,

Thanks for answering.

The registers are not memory mapped but reside inside the coprocessor.

I use an asm volatile inline-assembler code block to read them, so the
compiler can't optimize them out. I also checked the disassembly to make
sure everything compiles as expected.. Looks fine so far..

Cheers,
Nils Pipenbrinck

Nils_Pipenbrinck1 · November 9, 2009, 11:59pm

deepakvr@gmail.com wrote:

can this thread give some insights?

http://groups.google.com/group/beagleboard/browse_thread/thread/c47fc5c864576a7a/ba8421d3df1b35bc?hl=en&lnk=gst&q=performance+counters#ba8421d3df1b35bc

Thanks a lot.

I've tried the code, but it has exactly the same problem as mine. The
thread also shows that I'm not the first one who has these problems. I
can access the performance-counters (no exceptions generated), but they
never increase in value.

After some further digging I found out that there are two bits that
further control access to performance counters. It's NIDEN and DBGEN.
After boot these are zero. I checked that via one of the CP14 debug
registers.

Digging deeper:

DBGEN is not a bit in some register but a signal. Seems like I need a
JTAG-devide to set it.

NIDEN otoh is a ordinary register bit. I could set it in the "Secure
Debug Enable Register" of CP15. Unfortunately I need secure privileged
mode to do so.

Twiddeling this bit from a kernel-module results in exceptions. Guess
I'm not secure or privileged enough at the moment.

Any idea how to execute code in this secure mode? I thought executing
stuff from the kernel is the most privileged thing I could do.

Cheers,
Nils Pipenbrinck

yuli · November 23, 2009, 8:52am

I'm running the code NOT under linux, but with code-composer, and here
what works for me:

int Counter_uSec = 0;

void counters_init( void )
{
  int pmuserenr=0;
  int pmcr=0;
  pmuserenr = readPMUSERENR();
  writePMCR_Ebit(1); /* enable the A8 counters */
  writePMCR_Dbit(0); /* no clock divider */
  pmcr = readPMCR();
  enableCycleCounter();
  writePMCNTENSET_eventCounters(0xf); /* enable all the user counters
*/
  setupEventCounter(Counter0, EventTypeInstructions);
  setupEventCounter(Counter1, EventTypeICacheMisses);
  setupEventCounter(Counter2, EventTypeDCacheMisses);
  setupEventCounter(Counter3, EventTypeCycleCount);
  Counter_uSec = 0;
  resetAllCounters();
}

;****************************************************************
int GetCounter( void )
{
    unsigned int c2 = readCycleCounter();
    resetAllCounters();
    c2 = c2 / 484; // 331;
    Counter_uSec += c2;
    return c2;
}

;****************************************************************
;****************************************************************
;****************************************************************
;****************************************************************
.global _writePMCR_Ebit
_writePMCR_Ebit:
mrc p15, #0, r1, c9, c12, #0

    AND r0,r0,#0x3
    BIC r1,r1,#0x3
    ORR r1,r1,r0
  mcr p15, #0, r1, c9, c12, #0
  bx lr

;****************************************************************
  .global _readPMUSERENR
_readPMUSERENR:
  mrc p15, #0, r0, c9, c14, #0
  bx lr

;****************************************************************
; unsigned int readPMCR(void)
; Read the Performance Monitor Control Register
  .global _readPMCR
_readPMCR:
  mrc p15, #0, r0, c9, c12, #0
  bx lr

;****************************************************************
; void enableCycleCounter(void)
; enable the cycle counter register
  .global _enableCycleCounter
_enableCycleCounter:
  mov r1, #1
  mov r1, r1, lsl #31
  mrc p15, #0, r0, c9, c12, #1
  orr r0, r0, r1
  mcr p15, #0, r0, c9, c12, #1
  bx lr

;****************************************************************
; void writePMCNTENSET_eventCounters(int eventCounters)
; Write to Count Enable Set Register event counters (PMCNTENSET)
  .global _writePMCNTENSET_eventCounters
_writePMCNTENSET_eventCounters:
  ; was bug...need high order bit set to enable counter
  orr r0,r0, #0x80000000
  mcr p15, #0, r0, c9, c12, #1
  bx lr

;****************************************************************
; void setupEventCounter(int eventNumber, int eventType)
; setup event number to type of event to count
  .global _setupEventCounter
_setupEventCounter:
  mcr p15, #0, r0, c9, c12, #5
  mcr p15, #0, r1, c9, c13, #1
  bx lr

;****************************************************************
; void resetAllCounters(void)
; Reset all counters including the cycle counter
; Write to the Performance Monitor Control Register C-bit and P-bits,
bit[3:2]
  .global _resetAllCounters
_resetAllCounters:
  mrc p15, #0, r1, c9, c12, #0
  orr r1, r1, #0x6 ; set C, E bits to 1 - 'P=clear user counters',
C="clear clock counter'
  mcr p15, #0, r1, c9, c12, #0 ; reset the counters
  bx lr

;****************************************************************
; unsigned int readCycleCounter(void)
; read cycle counter register
  .global _readCycleCounter
_readCycleCounter:
  mrc p15, #0, r0, c9, c13, #0
  bx lr

Yuli Kaplunovsky
yk@magniel.com
+1 408 884 5965

yuli · November 23, 2009, 8:53am