Parallel LCD without vsync and hsync

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1

I am trying to interface an LCD to the beagle board, but my display
(AUO G057VN01, 6.5" 640x480) does not have hsync and vsync signals.
The interface to the display is 6 bits for each color, pixel clock,
and DE. The spec sheet descibes the required active and balnking
periods for the DE line for the horizontal and vertical scanning, but
there is nothing mentioned about hsync and vsync and there are no
hsync or vsync signals listed anywhere on the 33 pin connector.

I am trying to copy one of the example display drivers in drivers/
video/omap2/displays. It looks like the critical information is
defined in the following structure. How would I modify this to drive
a display without hsync and vsync signals? What are the hsw, hfp, hbp
parameters?

static struct omap_video_timings sharp_lq_timings = {
          .x_res = 480,
          .y_res = 272,

          .pixel_clock = 9000,

          .hsw = 42,
          .hfp = 3,
          .hbp = 2,

          .vsw = 11,
          .vfp = 3,
          .vbp = 2,
;

2

HI!

I worked with such panels. You don’t have to specify anything regarding HS/VS. Just make all others parameters correct for LCD timings

Max

2010/5/27 dcraw101 <dcraw101@gmail.com>

3

Great, do you know off hand what the hsw, hfp, and hbp parameters
are? I am guessing these are the critical timing parameters related
to horizontal and vertical scanning.

4

What are the hsw, hfp, hbp
parameters?

hfp = Front Porch = time slot between end of line and sync pulse
(Porch - Wikipedia)
hsw = Sync Width = width of sync pulse
hbp = Back Porch = time slot between sync pulse and start of next line
(i.e. next DE)

5

Sally,

your question is not correct because these parameters are described in a respective LCD datasheet and usually are unique for each display.
Please download this document and you will find all answers to your questions:
http://document.sharpsma.com/files/Interfacing_LCD_Panels071607a.pdf

regards,
Max

2010/5/28 Sally Crawford <crawford.sally@gmail.com>

6

from what i see,
AUO G057VN01 is a 5.7 inch panel. not a 6.5 inch.
and it seems that the timing for HSYNC, VSYNC is generated internally
in the LCD module..
so you only need to ensure the dot clock falls withiin 23.9 to 34.2MHz
and the DE signals are being generated correctly according to the
datasheet.

Look at Section
6.5 TFT- LCD Interface Timing
6.5.1

you might get the answer in the table there

KP

7

Hi I am sorry i meant look at the datasheet for AUO G057VN01 6.5.1 section

Look at Section
6.5 TFT- LCD Interface Timing
6.5.1

KP