PocketBeagle 2 ethernet cape

General Discussion
21

Hello everyone,

I’m trying to achieve the exact same result: using P1.02 instead of P2.03

I was able to remove the -22 (invalid argument) error with this overlay:

// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
 * DT Overlay for eth-wiz-click connections within the expansion header.
 *
 * https://www.mikroe.com/eth-wiz-click
 * https://download.mikroe.com/documents/add-on-boards/click/eth-wiz/eth-wiz-click-manual-v100.pdf
 *
 * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
 *
 */

/dts-v1/;
/plugin/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "ti/k3-pinctrl.h"

/*
 * Helper to show loaded overlays under: /proc/device-tree/chosen/overlays/
*/
&{/chosen} {
	overlays {
		k3-am62-pocketbeagle2-spi2-eth-wiz-click.kernel = __TIMESTAMP__;
	};
};

&main_pmx0 {
	w5500_rst_pin: pinmux_w5500_rst_pin {
		pinctrl-single,pins = <
			AM62X_IOPAD(0x01a8, PIN_DISABLE, 7) /* P1.04:  (D20) MCASP0_AFSX.GPIO1_12 RESET */
			AM62X_IOPAD(0x016C, PIN_INPUT, 7)   /* P1.04A: (Y18) RGMII2_TD0.GPIO0_89> */
		>;
	};

	w5500_irq_pin: pinmux_w5500_irq_pin {
		pinctrl-single,pins = <
			AM62X_IOPAD(0x01A0, PIN_DISABLE, 7) /* P1.02:  (E18)  MCASP0_AXR0.GPIO1_10 INT */
			AM62X_IOPAD(0x0164, PIN_INPUT, 7)   /* P1.02A: (AA19) RGMII2_TX_CTL.GPIO0_87 */
		>;
	};

	pb_spi2_pins: pinmux_pb_spi2_pins {
		pinctrl-single,pins = <
			AM62X_IOPAD(0x01ac, PIN_OUTPUT, 1) /* P1.06:  (E19) MCASP0_AFSR.SPI2_CS0 */
			AM62X_IOPAD(0x01b0, PIN_OUTPUT, 1) /* P1.08:  (A20) MCASP0_ACLKR.SPI2_CLK */
			AM62X_IOPAD(0x0194, PIN_INPUT, 1)  /* P1.10A: (B19) MCASP0_AXR3.SPI2_D0 */
			AM62X_IOPAD(0x0198, PIN_OUTPUT, 1) /* P1.12:  (A19) MCASP0_AXR2.SPI2_D1 */

			AM62X_IOPAD(0x0140, PIN_DISABLE, 7) /* P1.06A: (AD18) RGMII1_TD3.GPIO0_78 PIN_DISABLE */
			AM62X_IOPAD(0x01f0, PIN_DISABLE, 7) /* P1.10:  (A18)  EXT_REFCLK1.GPIO1_30 PIN_DISABLE */
			AM62X_IOPAD(0x013c, PIN_DISABLE, 7) /* P1.12A: (AE18) RGMII1_TD2.GPIO0_77 PIN_DISABLE */
		>;
	};
};

&main_spi2 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&pb_spi2_pins>;

	#address-cells = <1>;
	#size-cells = <0>;
	
	w5500: ethernet@0 {
		compatible = "wiznet,w5500";
		pinctrl-names = "default";
		pinctrl-0 = <&w5500_irq_pin>, <&w5500_rst_pin>;
		reg = <0x0>;
		interrupt-parent = <&main_gpio0>;
		interrupts = <87 IRQ_TYPE_EDGE_FALLING>;
		spi-max-frequency = <24000000>;
		local-mac-address = [ 00 00 00 00 00 00 ];
	};

	// Messing around with spidev, uncomment to show in /dev/spidev2.{0,1}
	// channel@0 {
	//     #address-cells = <1>;
	//     #size-cells = <0>;

	//     compatible = "rohm,dh2228fv";
	//     symlink = "bone/spi/2.0";

	//     reg = <0>;
	//     spi-max-frequency = <24000000>;
	//     spi-cpha;
	// };

	// channel@1 {
	//     #address-cells = <1>;
	//     #size-cells = <0>;

	//     compatible = "rohm,dh2228fv";
	//     symlink = "bone/spi/2.1";

	//     reg = <1>;
	//     spi-max-frequency = <24000000>;
	// };
};
Diff 
--- ./src/arm64/overlays/k3-am62-pocketbeagle2-spi2-eth-wiz-click.dtso	2025-05-12 15:41:08.516104250 +0200
+++ ./src/arm64/overlays/k3-am62-pocketbeagle2-spi2-eth-wiz-click-custom-5.dtso	2025-05-21 17:17:30.734843662 +0200
@@ -26,30 +26,30 @@
 };
 
 &main_pmx0 {
-	techlab_rst_pin: techlab-rst-default-pin {
+	w5500_rst_pin: pinmux_w5500_rst_pin {
 		pinctrl-single,pins = <
-			AM62X_IOPAD(0x01a8, PIN_DISABLE, 7) /* P1.04: (D20) MCASP0_AFSX.GPIO1_12 RESET */
-			AM62X_IOPAD(0x016c, PIN_OUTPUT, 7) /* P1.04: (Y18) RGMII2_TD0.GPIO0_89 RESET */
+			AM62X_IOPAD(0x01a8, PIN_DISABLE, 7) /* P1.04:  (D20) MCASP0_AFSX.GPIO1_12 RESET */
+			AM62X_IOPAD(0x016C, PIN_INPUT, 7)   /* P1.04A: (Y18) RGMII2_TD0.GPIO0_89> */
 		>;
 	};
 
-	techlab_irq_pin: techlab-irq-default-pin {
+	w5500_irq_pin: pinmux_w5500_irq_pin {
 		pinctrl-single,pins = <
-			AM62X_IOPAD(0x015c, PIN_INPUT, 7) /* P2.03: (AB22) MDIO0_MDIO.GPIO0_85 INT */
-			AM62X_IOPAD(0x019c, PIN_DISABLE, 7) /* P2.03: (B18) MCASP0_AXR1.GPIO1_9 INT */
+			AM62X_IOPAD(0x01A0, PIN_DISABLE, 7) /* P1.02:  (E18)  MCASP0_AXR0.GPIO1_10 INT */
+			AM62X_IOPAD(0x0164, PIN_INPUT, 7)   /* P1.02A: (AA19) RGMII2_TX_CTL.GPIO0_87 */
 		>;
 	};
 
-	techlab_spi_pins: techlab-spi-default-pins {
+	pb_spi2_pins: pinmux_pb_spi2_pins {
 		pinctrl-single,pins = <
-			AM62X_IOPAD(0x01b0, PIN_OUTPUT, 1) /* P1.06: (A20) MCASP0_ACLKR.SPI2_CLK */
-			AM62X_IOPAD(0x01ac, PIN_OUTPUT, 1) /* P1.08: (E19) MCASP0_AFSR.SPI2_CS0 */
-			AM62X_IOPAD(0x0194, PIN_INPUT, 1)  /* P1.10: (B19) MCASP0_AXR3.SPI2_D0 (MISO) */
-			AM62X_IOPAD(0x0198, PIN_OUTPUT, 1) /* P1.12: (A19) MCASP0_AXR2.SPI2_D1 (MOSI) */
-
-			AM62X_IOPAD(0x0140, PIN_DISABLE, 7) /* P1.06: (AD18) RGMII1_TD3.GPIO0_78 PIN_DISABLE */
-			AM62X_IOPAD(0x01f0, PIN_DISABLE, 7) /* P1.10: (A18) EXT_REFCLK1.GPIO1_30 PIN_DISABLE */
-			AM62X_IOPAD(0x013c, PIN_DISABLE, 7) /* P1.12: (AE18) RGMII1_TD2.GPIO0_77 PIN_DISABLE */
+			AM62X_IOPAD(0x01ac, PIN_OUTPUT, 1) /* P1.06:  (E19) MCASP0_AFSR.SPI2_CS0 */
+			AM62X_IOPAD(0x01b0, PIN_OUTPUT, 1) /* P1.08:  (A20) MCASP0_ACLKR.SPI2_CLK */
+			AM62X_IOPAD(0x0194, PIN_INPUT, 1)  /* P1.10A: (B19) MCASP0_AXR3.SPI2_D0 */
+			AM62X_IOPAD(0x0198, PIN_OUTPUT, 1) /* P1.12:  (A19) MCASP0_AXR2.SPI2_D1 */
+
+			AM62X_IOPAD(0x0140, PIN_DISABLE, 7) /* P1.06A: (AD18) RGMII1_TD3.GPIO0_78 PIN_DISABLE */
+			AM62X_IOPAD(0x01f0, PIN_DISABLE, 7) /* P1.10:  (A18)  EXT_REFCLK1.GPIO1_30 PIN_DISABLE */
+			AM62X_IOPAD(0x013c, PIN_DISABLE, 7) /* P1.12A: (AE18) RGMII1_TD2.GPIO0_77 PIN_DISABLE */
 		>;
 	};
 };
@@ -57,19 +57,43 @@
 &main_spi2 {
 	status = "okay";
 	pinctrl-names = "default";
-	pinctrl-0 = <&techlab_spi_pins>;
+	pinctrl-0 = <&pb_spi2_pins>;
 
 	#address-cells = <1>;
 	#size-cells = <0>;
-
+	
 	w5500: ethernet@0 {
 		compatible = "wiznet,w5500";
 		pinctrl-names = "default";
-		pinctrl-0 = <&techlab_irq_pin>, <&techlab_rst_pin>;
+		pinctrl-0 = <&w5500_irq_pin>, <&w5500_rst_pin>;
 		reg = <0x0>;
 		interrupt-parent = <&main_gpio0>;
-		interrupts = <85 IRQ_TYPE_EDGE_FALLING>;
+		interrupts = <87 IRQ_TYPE_EDGE_FALLING>;
 		spi-max-frequency = <24000000>;
 		local-mac-address = [ 00 00 00 00 00 00 ];
 	};
-};
\ No newline at end of file
+
+	// Messing around with spidev, uncomment to show in /dev/spidev2.{0,1}
+	// channel@0 {
+	//     #address-cells = <1>;
+	//     #size-cells = <0>;
+
+	//     compatible = "rohm,dh2228fv";
+	//     symlink = "bone/spi/2.0";
+
+	//     reg = <0>;
+	//     spi-max-frequency = <24000000>;
+	//     spi-cpha;
+	// };
+
+	// channel@1 {
+	//     #address-cells = <1>;
+	//     #size-cells = <0>;
+
+	//     compatible = "rohm,dh2228fv";
+	//     symlink = "bone/spi/2.1";
+
+	//     reg = <1>;
+	//     spi-max-frequency = <24000000>;
+	// };
+};

But I am still not able to get it to work. Could anyone with more of an idea of how SPI works chip in?

Kind regards,

Joery

22

when testing spi with eeproms, it needed “ti,pindir-d0-out-d1-in;” in the main_spi2 location
also, you might need
ti,spi-num-cs = <1>;
depending on which CS your using, if CS0 then “1” should be ok

23

@Joery123123 @Cas_Bremer
i don’t have a wiznet click, but i do have a wiz850io module
on PB2, getting the
w5100 spi0.0: probe with driver w5100 failed with error -22
genirq: Setting trigger mode 8 for irq 389 failed (gpio_irq_type+0x0/0x20)

on BBB, it works, 5.6Mb/s per iperf
on RPI0, it works, 11Mb/s per iperf

on PB2, the INTn pin never goes low and only get the soft reset command sent once when the driver is loaded.
JMO, think there are issues with the PB2 interrupts, or maybe just the dts interrupt configuration

24

Anything new on this subject?