PWM Subsystem Time Base input clock frequency?

According to the TRM, the Time Base module on each of the PWM subsystems is clocked directly from the cpu clock. That is, its being clocked at a period of 1 nsec. It can be prescaled down to 1/128,for a period of 128 nsecs. The period and the counter compare registers are only 16 bits wide so the minimum PWM frequency is about 120 MHz. Is that correct?

Bob Stewart

I guess I would argue that with 16 bits the counter can count up to 65535 and wrap around after 65536 counts of 128ns max. That gives a max period of the PWM of 8.39ms and a min frequency of 119Hz - I think. But it has been a long day, so I might very well be very wrong :wink:

   Peter

sigh...thanks, you are correct. But, it is fast than I would have expected.

Sigh...you are correct! But it's still a higher frequency than I expected for the slowest PWM signal. I thought that the input clock might not be at the cpu frequency.
Thanks.

According to the TRM, the Time Base module on each of the PWM
subsystems is clocked directly from the cpu clock. That is, its being
clocked at a period of 1 nsec.

Where exactly are you seeing this? Virtually nothing on the chip but
the ARM cores and directly connected caches will be running at 1 GHz.

I show the PWMSS to be clocked by the L4 interconnect clock (see section
15.1.2.2) with a maximum functional clock frequency of 100 MHz (15.1.2.3).

The L4_PER domain the PWM units are all connected to is for "slow"
peripherals. The L4_Fast domain used for the PRU is only 200 MHz, and
I'd be surprised if you could configure the L4_PER clock to be over 100
MHz (but I haven't crawled through all the clock routing and power
management logic to prove this).

It can be prescaled down to 1/128,for
a period of 128 nsecs. The period and the counter compare registers
are only 16 bits wide so the minimum PWM frequency is about 120 MHz.
Is that correct?

Take all your GHz numbers and divide by 10 for the actual 100 Mhz clock
frequency.

Thanks for the reply, Charles. That makes sense.

Table 15-12 on page 2006 of the TRM refers to TBCLK being a prescaled version of SYSCLKOUT which is, later in that section, mentioned to be the cpu clock, or so I remembered.

Thanks very much.

Bob Stewart

CPU Friday, January 31, 2014 5:57:32 PM UTC-5, Charles Steinkuehler wrote:

Yes, it can be quite confusing.

For example, note (1) on Table 15-41 states:

(1) System frequency = SYSCLKOUT, that is, CPU clock. TBCLK = SYSCLKOUT

...but you have to realize each major section of the TRM is written
somewhat independently. These document various IP cores that mostly get
cut-and-pasted into various SoCs. If this was a Cortex M4 part (which
this IP core was likely designed for initially), it probably _would_ be
the CPU clock, but in this context they are actually referring to the
primary clock for the module, which on the AM335x comes from the L4
interconnect, not from the CPU.

Later on, note (1) from Table 15-42 states:

(1) System clock, SYSCLKOUT and TBCLK = 100 MHz, 10 ns

...which is much more believable.

Of course pretty much all the clock frequencies can be programmed, shut
down, and otherwise messed with in complicated ways. Unless you want to
crawl through the kernel clock tree code, testing is the easiest way to
see what frequency it's really running. Since the maximum supported
frequency is 100 MHz, I'd suspect that's what is getting setup by default.