Has anybody determined what speed the PRUs run at by default on the BBAI64?
Supposedly the PRU_ICSSGs are capable of 250MHz. Sec 1.4.2 (p 4858) PRU_ICSSG Getting Started Guide.
And, I’ve found documentation for the very similar AM65xx that corroborates this:
Section 6.5.3 PRU_ICSSG Integration in the AM65xx Technical Reference Manual:
The PRU cores supports three clock speeds — 200 MHz, 225 MHz (default), and 250 MHz. Below are the
basic register configurations required for enabling each clock speed:
• 200 MHz
– CTRLMMR_ICSSGn_CLKSEL[0] CORE_CLKSEL = 1 (CPSWHSDIV_CLKOUT2 is source clock)
– ICSSG_CORE_SYNC_REG[0] CORE_VBUSP_SYNC_EN = 0 (Async Mode, default)
• 225 MHz
– CTRLMMR_ICSSGn_CLKSEL[0] CORE_CLKSEL = 0 (PER1HSDIV_CLKOUT1, default)
– ICSSG_CORE_SYNC_REG[0] CORE_VBUSP_SYNC_EN = 0 (Async Mode, default)
• 250 MHz
– CTRLMMR_ICSSGn_CLKSEL[0] CORE_CLKSEL = don’t care
– ICSSG_CORE_SYNC_REG[0] CORE_VBUSP_SYNC_EN = 1 (Sync-to-VCLK Mode)
Clocked at 250MHz would yield 4ns resolution.
However TI it seems does improve on their numbers, and thus there’s a precedent that improvements are made to the PRUs to get faster clocks out of them. For example this passage from the AM243x documentation:
The Sitara Devices contain PRU Cores which are capable of executing instructions in a completely deterministic manner. The various clock speed options available are 200MHz, 225MHz, 250MHz, 300MHz, 333MHz giving us a resolution of upto 3ns. This allows us to use PRU Cores for realtime I/O control applications.
The question is was the PRU_ICSSGx improved in the J721E or is it a very close variant to the AM65x and thus can only be expected to go 250MHz?
If someone has an O-scope they can test this on, here’s a TI E2E thread where someone wrote a simple while-loop that would pulse an output at a known PRU execution rate to allow you to glean the PRU’s clock speed: