XRDY Interrupt is enabled.
I configure the Threshold value to 1Kbytes. Transmit buffer size is 5Kbytes.
The decoded audio samples(16 bit) will be written to Data transmit register one by one in a for loop.
After writing the each sample I read the XRDY bit of MCBSPLP_SPCR2_REG(serial port control register 2).
If not possible to write Rendering task shall wait on a semaphore.
Assumption: XRDY bit is zero because there is no free space in transmit buffer. When the free locations
in the transmit buffer goes above threshold value McBSP interrupts the CPU and in the interrupt handler
I shall release the semaphore for which the rendering task was waiting. Semaphore is used for
Soren, can you please check the new design. Am i missing anything?
I just went quickly through you question and I can’t see any obvious problems. As stated previously it has been some time since I have done any McBSP coding myself, but I think your approach as such is correct. It might be you mis a single bit here and there, but the general structure is correct – Just go for it J
I however have two comments:
Take care, there are two different XRDY bits – One in MCBSPLP_SPCR2_REG and one in MCBSPLP_IRQSTATUS_REG. I guess you already found this, but thought to mention it to be 100% sureJ
Dependent on the number of other tasks you need to run on the A8 core you might want a DMA channel to fill the McBSP buffer instead of having the A8 doing it? In this case you should program the McBSP to signal a DMA request “instead of”/”in addition to” an interrupt when it’s running low on data. This approach is better at ensuring the McBSP not under-running in case of “heavy system activity”/”disabled interrupts”/etc on the A8 core. Although 5KB might sound as a huge buffer it will for a 48KHz stereo signal only contain data for ~25ms J
Best regards – Good luck