some CAP development questions

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1

Hi

I tried to find the answers but probably they are not adressed.

  1. is the standard CAPE using 3 mounting holes and not 4? we just want to be sure. current docs say 3 mount holes, but some existing CAPEs already have 4 ?

  2. LCD_DATA(0…15) are also BOOT mode pins that have 100k pullup or pulldown on beagle bone, this means that the CAPES can not not have pullups/pulldown on those pins? As it may make the bone not to boot? This seems not being addressed in the documentation… like if we place an FPGA on CAPE then the FPGA may have default pullups on those pins, overriding the weak pulldown and changing boot mode…

  3. What is the minumum size for the ID EEPROM to be safe and compliant? can CAPEs designed today just have say 256 byte EEPROM if it is compatible with the protocol and addressing? I assume yes, because the CAPES should remain compatible, eg released capes with current ID EEPROM version should remain valid later? and currently less that 256 bytes are used

Antti

2

See below.

Gerald

Hi

I tried to find the answers but probably they are not adressed.

  1. is the standard CAPE using 3 mounting holes and not 4? we just want to be sure. current docs say 3 mount holes, but some existing CAPEs already have 4 ?

Does not matter. Most capes will require no mounting holes at all as the retention of the connectors is more than enough to prevent a Cape from falling off. Thre or four is your decsion.

  1. LCD_DATA(0…15) are also BOOT mode pins that have 100k pullup or pulldown on beagle bone, this means that the CAPES can not not have pullups/pulldown on those pins?

Not unless you plan to override the boot pins. Otherwise do not add pullups or pulldowns to these pins.

As it may make the bone not to boot?

That is correct.

This seems not being addressed in the documentation… like if we place an FPGA on CAPE then the FPGA may have default pullups on those pins, overriding the weak pulldown and changing boot mode…

Correct. Try not to add pullups or pulldowns.

  1. What is the minumum size for the ID EEPROM to be safe and compliant?

Read the System refernec eMnaubal. It tells the EEPROM to use. It must use 16 bit addressing. 8 bit will not work.

can CAPEs designed today just have say 256 byte EEPROM if it is compatible with the protocol and addressing?

No.

I assume yes, because the CAPES should remain compatible, eg released capes with current ID EEPROM version should remain valid later? and currently less that 256 bytes are used

Use the large size, otherwise it will not be 16b addressing. In order to have 16 bit addressing, it must be the larger size.

3

Hi

thanks for reply, but unfortunatly the questions are not fully answered.

If standard template exist then either 3 or 4 mounting holes should be specified in documentation, not use 3 or 4 or none…

BOOT mode pins, I do not want add pull down or pull ups, but in case I use IC that MAY have internall pullups enabled, then this may be a problem.

FPGA device in ERASE stata may have all pins as input with pullups enabled

I have intention to include small EEPROM, I was thinking using some other device inplace of EEPROM hence I said IF compatible, is then 256 bytes ok?

as example the FPGA or MCU on cape can emulate the EEPROM, but in that case it may be desirable to emulate less memory not 32K

sorry for asking clear responses, but if the SPEC are made properly, it is for everyones best interest.

also the EEPROM does not have to be 1M i2c compatible as the ARM itself only support 400khz not 1mhz mode. So emulating an 16 bit addressable 256 byte large eeprom would work…

Antti

4

See below.

Gerald

Hi

thanks for reply, but unfortunatly the questions are not fully answered.

If standard template exist then either 3 or 4 mounting holes should be specified in documentation, not use 3 or 4 or none…

There is no template. It is all up to the designer.

BOOT mode pins, I do not want add pull down or pull ups, but in case I use IC that MAY have internall pullups enabled, then this may be a problem.

Yest it may.

FPGA device in ERASE stata may have all pins as input with pullups enabled

Maybe you should use the GPMC signals instead of the LCD.

I have intention to include small EEPROM, I was thinking using some other device inplace of EEPROM hence I said IF compatible, is then 256 bytes ok?

It will NOT be OK. Because the small size is 8bit addressing, It must be one that has 16b addressing.

as example the FPGA or MCU on cape can emulate the EEPROM, but in that case it may be desirable to emulate less memory not 32K

As long as it is 16b adressing it will be OK.

sorry for asking clear responses, but if the SPEC are made properly, it is for everyones best interest.

16b adressing is required.

also the EEPROM does not have to be 1M i2c compatible as the ARM itself only support 400khz not 1mhz mode. So emulating an 16 bit addressable 256 byte large eeprom would work…

If you can do that then that should be fine. This is a SW issue and a SW requirement. One that was not my idea.