spi header pins

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1

Looks like SPI1 uses pins
P9_28(mode3) SPI1_CS0
P9_29(mode3) SPI1_D0
P9_30(mode3) SPI1_D1
P9_31(mode3) SPI1_SCLK
P9_42(mode2) or P9_19(mode4) SPI1_CS1 (opt, with proper pinmux)

the CS pins are clear enough as is the SCLK pin, but I only see SPI_D0 and SPI_D1 with no reference to MOSI or MISO. Which is which? Is there a typo in table 11 of the bone SRM where SPI_D1 really should be SPI_DI and SPI_D0 should be SPI_DO (or possibly even a font that could be clearer?

Eric

2

It deepnds on how you set up the SW registers. Either one can be an input. Either one can be an output.

Gerald

3

SPI0 is also pinned out in the P9 expansion header (pins 17,18,21,22),
although I _think_ only a single CS pin is available (I need to look
again at the muxing...).

Only thing to watch for is, at boot time if you're using SPI0 boot, the
am335x boot ROM expects D0 to be MISO and D1 to be MOSI. Section
26.1.7.2.7.4 in the am335x Technical Ref Manual (currently page 4577).
Most likely this doesn't apply to you if using the normal Bone boot
mode, but using that convention is probably worthwhile for compatibility
reasons.

-Andrew

4

While this is true, the part you no doubt want to know is that when the stock Beagle Bone kernel from TI is booted, D0 is MISO and D1 is MOSI.

From what I could tell, it’s not configured in any way in the kernel, but it may be configured from u-boot (I didn’t look).

Alan.

5

It is actually configured in the kernel in spi-omap2-mcspi.c function omap2_mcspi_setup_transfer() around line 677 - 678 (v3.3 1):

l &= ~(OMAP2_MCSPI_CHCONF_IS|OMAP2_MCSPI_CHCONF_DPE1);

l |= OMAP2_MCSPI_CHCONF_DPE0;

6

Yes, you are right.

I guess I missed it :frowning: