SPI in 48MHz

Hi
Am using Beagle Bone balck with angstrom. Working with SPI in 48MHz as a master.
if i send bytes am getting the following issues

  1. Delay between the first byte and second byte is around 18us
  2. Inter byte delay around 400ns
  3. cs hold time is around 127us

can someone please help me to reduce this

to what? setting SPI to higher clock?

Hi
Am using Beagle Bone balck with angstrom. Working with SPI in 48MHz as a master.
if i send bytes am getting the following issues

  1. Delay between the first byte and second byte is around 18us
  2. Inter byte delay around 400ns
  3. cs hold time is around 127us

can someone please help me to reduce this

Are you talking to SPI via SPIDEV or are you using a Kernel Module or Device driver?

Regards,
John

I don’t think you will be able to overcome these times using the existing SPI HW and SW. 48 MHz is the fastest the SPI hardware can run because that is the clock signal it gets before any clock dividing. Some things I have read say not to use it at faster than /3 (16 Mhz). If you really need to run faster, program a PRU to bitbang SPI: I think you could write fixed sequences out at 100 Mbits/second, if you can manage to get 100 MHz signals off the board without too much noise and ringing. (I would put 25 ohm resistors in series with the cs, clock, and mosi signals to terminate them.) Then you can have zero time between bytes, use whatever cs hold time you need, etc.