Testing FPGA connection to OMAP3

This is not strictly Beagle related, but I figured some of you might
be amused by this photo:

http://www.flickr.com/photos/32615155@N00/4109693393/

I'm trying to test connecting the GPMC controller to a FPGA. As I
connect more Address/data lines to the fpga, I start having trouble
with the network (root and kernel are loaded via the network). After
attaching about five lines, I start to see checksum errors loading the
kernel.

Does anyone know if the OMAP3 can drive the long lines attached to the
GPMC pins?

Philip

I am guessing that IMG_0196 contains the TI DLP pico projector that's
sold with the beagleboard?

I guess it depends on your definition of long. A couple of inches should not be an issue as long as nothing else is on the lines.

Gerald

I guess it depends on your definition of long. A couple of inches should not
be an issue as long as nothing else is on the lines.

The jumper wires from the logicpd board to the fpga board are seven
inches long ....

Philip

I suspected as much. Not to mention the load on the databus from the NAND I would buffer these signals, address and data, before running them too far.

Gerald

From: Philip Balister [mailto:philip.balister@gmail.com]
Sent: Monday, November 16, 2009 3:30 PM
To: beagleboard@googlegroups.com
Subject: Re: [beagleboard] Testing FPGA connection to OMAP3

> I guess it depends on your definition of long. A couple of inches should

not

> be an issue as long as nothing else is on the lines.

The jumper wires from the logicpd board to the fpga board are seven
inches long ....

I don’t think this will work, even if you buffer these lines. The problem is
the antenna effect, given the rise time for these signals and the length of
these lines. For each signal, look for the return path to ground. Looking at
your picture, I suspect that the area between the signal line and the return
path is large, causing all kinds of radiation and crosstalk. Also, the
impedance of each line is uncontrolled, so I would expect to see all kinds
of reflections. If you want to connect these boards, try flex PCB with
ground plane, or use 50 ohm coax to connect each line.

Philip

>
> Gerald
>
>>
>> > This is not strictly Beagle related, but I figured some of you might
>> > be amused by this photo:
>> >
>> > Current hacking | Philip Balister | Flickr
>> >
>>
>> I am guessing that IMG_0196 contains the TI DLP pico projector that's
>> sold with the beagleboard?
>>
>> --
>> Andrew Jackman
>> kd7nyq@gmail.com
>>
>> CONFIDENTIALITY NOTICE: This e-mail message, including any
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It depends on the speed the GPMC is being run at, not defined, and the voltage levels of the resulting signals, not defined. You can buffer these signals using LVDS or SERDES buffers resulting in differential pairs. A lot of FPGAs, not defined here, that have these interrfaces built in.

Gerald

It depends on the speed the GPMC is being run at, not defined, and the voltage levels of the resulting signals, not defined. You can buffer these signals using LVDS or SERDES buffers resulting in differential pairs. A lot of FPGAs, not defined here, that have these interrfaces built in.

I like the idea, but differential pairs have to be length matched and the line impedance controlled. Better to create a PCB and connect directly to the BeagleBoard.

Gerald

From: Philip Balister [mailto:philip.balister@gmail.com]
Sent: Monday, November 16, 2009 3:30 PM
To: beagleboard@googlegroups.com
Subject: Re: [beagleboard] Testing FPGA connection to OMAP3

I guess it depends on your definition of long. A couple of inches should
not
be an issue as long as nothing else is on the lines.

The jumper wires from the logicpd board to the fpga board are seven
inches long …

I don’t think this will work, even if you buffer these lines. The problem is
the antenna effect, given the rise time for these signals and the length of
these lines. For each signal, look for the return path to ground. Looking at
your picture, I suspect that the area between the signal line and the return
path is large, causing all kinds of radiation and crosstalk. Also, the
impedance of each line is uncontrolled, so I would expect to see all kinds
of reflections. If you want to connect these boards, try flex PCB with
ground plane, or use 50 ohm coax to connect each line.

Philip

Gerald

This is not strictly Beagle related, but I figured some of you might
be amused by this photo:

http://www.flickr.com/photos/32615155@N00/4109693393/

I am guessing that IMG_0196 contains the TI DLP pico projector that’s
sold with the beagleboard?


Andrew Jackman
kd7nyq@gmail.com

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destroy all copies of the original message. All your base are belong
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Just a note, this is a case of I have the logicpd board with exposed
gpmc and I have the FPGA board that I have configured for 1.8v IO. So
why not see if you can test the gpmc to fpga interface without laying
out a board.

Obviously, laying out a board is a much better approach :slight_smile:

Philip

A PCB is always the best solution.

Gerald

From: Philip Balister [mailto:philip.balister@gmail.com]
Sent: Tuesday, November 17, 2009 4:55 AM
To: beagleboard@googlegroups.com
Subject: Re: [beagleboard] Testing FPGA connection to OMAP3

Just a note, this is a case of I have the logicpd board with exposed
gpmc and I have the FPGA board that I have configured for 1.8v IO. So
why not see if you can test the gpmc to fpga interface without laying
out a board.

This is certainly possible, but it is the way you connect the boards
together that matters. If you have used an oscilloscope to measure high
speed signals, you will know that you cannot use a probe with a 2 or 3 inch
ground wire as it will pickup noise from adjacent circuits and this has
fooled many inexperienced engineers into thinking there is noise on that
data line. We use special adaptors to minimize the distance between the
probe pin and the ground pin of the probe. I'm not about to start explaining
Electro Magnetic Compatibility (EMC) or Signal Integrity (SI) principles,
but the easiest way to think about a good approach is to measure the area
between the signal line and the return ground line as shown in this diagram.

--------------------------------

Signal ------------------------------------------| Data1
           //////////////////////////////////////// |
Ground ----------------------------------------| GND

---------------------------------

The // represents the area that must be minimized to prevent the antenna
effect (causes radiation and crosstalk). I ideally you want to run each
signal line and it's return ground line next to each other to minimize the
area and also to control the impedance of the line. While I have never tried
to do this, this should work. Use a small RF connector, something like an
UFL for each signal line on both boards and then use a coaxial patch cable
to connect each signal. Search for UFL on Digikey to see these parts.

Ultimately, it will probably be easier to just layout a PCB and avoid any
uncertainty and risk.

I hope this helps.

Obviously, laying out a board is a much better approach :slight_smile:

Philip

>
>
> From: Gerald Coley [mailto:gerald@beagleboard.org]
> Sent: Monday, November 16, 2009 4:43 PM
> To: beagleboard@googlegroups.com
> Subject: Re: [beagleboard] Testing FPGA connection to OMAP3
>
>
>
> It depends on the speed the GPMC is being run at, not defined, and the
> voltage levels of the resulting signals, not defined. You can buffer

these

> signals using LVDS or SERDES buffers resulting in differential pairs. A

lot

> of FPGAs, not defined here, that have these interrfaces built in.
>
> I like the idea, but differential pairs have to be length matched and

the

> line impedance controlled. Better to create a PCB and connect directly

to

> the BeagleBoard.
>
>
>
> Gerald
>
>
>> From: Philip Balister [mailto:philip.balister@gmail.com]
>> Sent: Monday, November 16, 2009 3:30 PM
>> To: beagleboard@googlegroups.com
>> Subject: Re: [beagleboard] Testing FPGA connection to OMAP3
>>
>> > I guess it depends on your definition of long. A couple of inches

should

> not
>> > be an issue as long as nothing else is on the lines.
>>
>> The jumper wires from the logicpd board to the fpga board are seven
>> inches long ....
>
> I don’t think this will work, even if you buffer these lines. The

problem is

> the antenna effect, given the rise time for these signals and the length

of

> these lines. For each signal, look for the return path to ground.

Looking at

> your picture, I suspect that the area between the signal line and the

return

> path is large, causing all kinds of radiation and crosstalk. Also, the
> impedance of each line is uncontrolled, so I would expect to see all

kinds

> of reflections. If you want to connect these boards, try flex PCB with
> ground plane, or use 50 ohm coax to connect each line.
>
>>
>> Philip
>>
>> >
>> > Gerald
>> >
>> >>
>> >> > This is not strictly Beagle related, but I figured some of you

might

>> >> > be amused by this photo:
>> >> >
>> >> > Current hacking | Philip Balister | Flickr
>> >> >
>> >>
>> >> I am guessing that IMG_0196 contains the TI DLP pico projector

that's

>> >> sold with the beagleboard?
>> >>
>> >> --
>> >> Andrew Jackman
>> >> kd7nyq@gmail.com
>> >>
>> >> CONFIDENTIALITY NOTICE: This e-mail message, including any
>> >> attachments, is for the sole use of the intended recipient(s) and

may

>> >> contain confidential and privileged information. Any unauthorized
>> >> review, use, disclosure, or distribution is prohibited. If you are

not

>> >> the intended recipient, please contact the sender by reply e-mail

and

>> >> destroy all copies of the original message. All your base are

belong

>> >> to us.
>> >>
>> >> --
>> >>
>> >> You received this message because you are subscribed to the Google
> Groups
>> >> "Beagle Board" group.
>> >> To post to this group, send email to beagleboard@googlegroups.com.
>> >> To unsubscribe from this group, send email to
>> >> beagleboard+unsubscribe@googlegroups.com.
>> >> For more options, visit this group at
>> >> http://groups.google.com/group/beagleboard?hl=.
>> >>
>> >>
>> >
>> > --
>> >
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>> >
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>
>
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Here is an even better explanation of why this won't work.

http://www.sigcon.com/Pubs/news/2_8.htm

John (USP) wrote:

From: John (USP) [mailto:jsynesio@us-power.com]
Sent: Tuesday, November 17, 2009 9:59 AM
To: beagleboard@googlegroups.com
Subject: RE: [beagleboard] Testing FPGA connection to OMAP3

> From: Philip Balister [mailto:philip.balister@gmail.com]
> Sent: Tuesday, November 17, 2009 4:55 AM
> To: beagleboard@googlegroups.com
> Subject: Re: [beagleboard] Testing FPGA connection to OMAP3
>
> Just a note, this is a case of I have the logicpd board with exposed
> gpmc and I have the FPGA board that I have configured for 1.8v IO. So
> why not see if you can test the gpmc to fpga interface without laying
> out a board.

Here is an even better explanation of why this won't work.

Wire-Wrap

and this one is a must read:

From: Vladimir Pantelic [mailto:pan@nt.tu-darmstadt.de]
Sent: Wednesday, November 18, 2009 6:06 AM
To: beagleboard@googlegroups.com; Philip Balister
Subject: Re: [beagleboard] Testing FPGA connection to OMAP3

John (USP) wrote:
>
>
>> From: John (USP) [mailto:jsynesio@us-power.com]
>> Sent: Tuesday, November 17, 2009 9:59 AM
>> To: beagleboard@googlegroups.com
>> Subject: RE: [beagleboard] Testing FPGA connection to OMAP3
>>
>>
>> > From: Philip Balister [mailto:philip.balister@gmail.com]
>> > Sent: Tuesday, November 17, 2009 4:55 AM
>> > To: beagleboard@googlegroups.com
>> > Subject: Re: [beagleboard] Testing FPGA connection to OMAP3
>> >
>> > Just a note, this is a case of I have the logicpd board with

exposed

>> > gpmc and I have the FPGA board that I have configured for 1.8v IO.

So

>> > why not see if you can test the gpmc to fpga interface without

laying

>> > out a board.
>
> Here is an even better explanation of why this won't work.
>
> Wire-Wrap

and this one is a must read:

Amazon.de

Agreed. This book is written by the same author, Howard Johnson who is
considered one of the foremost authorities in this area. Howard's seminars
on high speed digital design are very enlightening and it anyone is
interested, got to his website www.sigcon.com

> Amazon.de
Agreed. This book is written by the same author, Howard Johnson who is
considered one of the foremost authorities in this area. Howard's
seminars
on high speed digital design are very enlightening and it anyone is
interested, got to his website www.sigcon.com

Agree, the above book is great (though containing some (important) typos, so
take care). Another set of books I can strongly recommend are: "Right the
First Time Volume 1 & 2" by Lee Ritchey
(http://www.speedingedge.com/rtft_book.htm), who is another of the
US-High-Speed-Gurus :slight_smile:

I find these books a bit more "practical" that the one by Howard. But in
general I can strongly recommend all three of them and tend to say, that all
3 books are must reads in case one want to do serious High Speed PCB
designs.

That being said - Asking Philip to read tons of pages doesn't bring him
forward with his FGPA project, but it of cause tells him why his current
setup is failing and why it's definitely recommendable to do such things in
a "controlled setup" - I totally agree :slight_smile:

One way to go forward is to slow all GPMC access (NAND, Ethernet and FPGA).
You can do this most easily by reducing the general GPMC-clock(s) - I can't
remember if it's a single divider in the GPMC module or if it's set on a
CS-basis. I don't know if this brings any value to your FPGA testing (or you
need to run at full speed?), but it's definitely a way forward...

You won't get rid of the Reflections/Signal Integrity problems, since the
edges of the transitions on the GPMC-bus will still be fast, although
lowering the general clock speed. But since you are now working in a slower
speed, the reflections will have time to reach steady state before the OMAP
(or device on the GPMC bus) will sample (and use) the signal, thereby making
your system functional. Straight out of my mind I would expect a signaling
rate of ~20-30MHz to be OK (since 7 inch wire have around 2-3ns of roundtrip
signal traveling time, which is much less than the 33-50ns for the 20-30MHz
clock)

Good luck
  Søren

You can CS based configuration also (GPMC_CONFIG0-7 worth of them). in
some cases, it is a major pain in the backend to do it though..
a) I wonder the CONTROL_PROG_IO could be used to control the drive strength..
b) as I recollect, L3 clk(165Mhz) is the functional clock for gpmc. so
you'd have to play with the individual signal widths.
Regards,
NM

a) I wonder the CONTROL_PROG_IO could be used to control the drive
strength..

This will definitely be an option to discover as well (and thanks for
pointing me to the register - I couldn't find it when I did a quick search
for it :-(). Give it a try and see what the scope tells...

b) as I recollect, L3 clk(165Mhz) is the functional clock for gpmc. so
you'd have to play with the individual signal widths.

I think you are right on that as well
  Søren

From: Søren Steen Christensen [mailto:lists@ssc-solutions.dk]
Sent: Wednesday, November 18, 2009 12:30 PM
To: beagleboard@googlegroups.com
Subject: RE: [beagleboard] Testing FPGA connection to OMAP3

> > Amazon.de
> Agreed. This book is written by the same author, Howard Johnson who is
> considered one of the foremost authorities in this area. Howard's
> seminars
> on high speed digital design are very enlightening and it anyone is
> interested, got to his website www.sigcon.com

Agree, the above book is great (though containing some (important) typos,

so

take care). Another set of books I can strongly recommend are: "Right the
First Time Volume 1 & 2" by Lee Ritchey
(http://www.speedingedge.com/rtft_book.htm), who is another of the
US-High-Speed-Gurus :slight_smile:

Søren, good point. Howard Johnson's book was printed in 1993, so it is
getting a little old, but I still find it relevant even today.

I find these books a bit more "practical" that the one by Howard. But in
general I can strongly recommend all three of them and tend to say, that

all

3 books are must reads in case one want to do serious High Speed PCB
designs.

That being said - Asking Philip to read tons of pages doesn't bring him
forward with his FGPA project, but it of cause tells him why his current
setup is failing and why it's definitely recommendable to do such things

in

a "controlled setup" - I totally agree :slight_smile:

One way to go forward is to slow all GPMC access (NAND, Ethernet and

FPGA).

You can do this most easily by reducing the general GPMC-clock(s) - I

can't

remember if it's a single divider in the GPMC module or if it's set on a
CS-basis. I don't know if this brings any value to your FPGA testing (or

you

need to run at full speed?), but it's definitely a way forward...

You won't get rid of the Reflections/Signal Integrity problems, since the
edges of the transitions on the GPMC-bus will still be fast, although
lowering the general clock speed. But since you are now working in a

slower

speed, the reflections will have time to reach steady state before the

OMAP

(or device on the GPMC bus) will sample (and use) the signal, thereby

making

your system functional. Straight out of my mind I would expect a signaling
rate of ~20-30MHz to be OK (since 7 inch wire have around 2-3ns of

roundtrip

signal traveling time, which is much less than the 33-50ns for the

20-30MHz

clock)

Another approach is to slow down the edge transition using series resistors.
The article I referenced previously talks about this approach.

All this hardware design stuff must be driving these Linux gurus crazy :wink:

Well I don’t mind being just ‘basic’ but

  • try twisting the wires, maybe with a slightly different pitch from each other and each one with a ground line. This helps reducing crosstalk quite a bit.
  • consider re-checking that the FPGA input lines are properly configured

I don’t thing you are working in a EMI polluted environemnt and so the clock-rates we are talking about shoudl not be a issue.
In the case this still won’t work

  • use some ferrite bead, try first on the FPGA side, eventually on both.